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AD9883AKSTZ-140 PDF Datasheet浏览和下载

型号:
AD9883AKSTZ-140
PDF下载:
下载PDF文件 在线浏览文档
内容描述:
110 MSPS / 140 MSPS模拟接口用于平板显示器 [110 MSPS/140 MSPS Analog Interface for Flat Panel Displays]
文件大小:
223 K
文件页数:
28 Pages
品牌Logo:
品牌名称:
AD [ ANALOG DEVICES ]



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a
FEATURES
Industrial Temperature Range Operation
140 MSPS Maximum Conversion Rate
300 MHz Analog Bandwidth
0.5 V to 1.0 V Analog Input Range
500 ps p-p PLL Clock Jitter at 110 MSPS
3.3 V Power Supply
Full Sync Processing
Sync Detect for Hot Plugging
Midscale Clamping
Power-Down Mode
Low Power: 500 mW Typical
4:2:2 Output Format Mode
APPLICATIONS
RGB Graphics Processing
LCD Monitors and Projectors
Plasma Display Panels
Scan Converters
Microdisplays
Digital TV
110 MSPS/140 MSPS Analog Interface
for Flat Panel Displays
AD9883A
FUNCTIONAL BLOCK DIAGRAM
R
AIN
CLAMP
A/D
8
R
OUTA
G
AIN
CLAMP
A/D
8
G
OUTA
B
AIN
CLAMP
A/D
8
B
OUTA
MIDSCV
HSYNC
COAST
CLAMP
FILT
SYNC
PROCESSING
AND CLOCK
GENERATION
DTACK
HSOUT
VSOUT
SOGOUT
REF
REF
BYPASS
SCL
SDA
A
0
SERIAL REGISTER
AND
POWER MANAGEMENT
AD9883A
GENERAL DESCRIPTION
The AD9883A is a complete 8-bit, 140 MSPS, monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 140 MSPS encode
rate capability and full power analog bandwidth of 300 MHz
supports resolutions up to SXGA (1280
×
1024 at 75 Hz).
The AD9883A includes a 140 MHz triple ADC with internal
1.25 V reference, a PLL, and programmable gain, offset, and
clamp control. The user provides only a 3.3 V power supply,
analog input, and Hsync and COAST signals. Three-state
CMOS outputs may be powered from 2.5 V to 3.3 V.
The AD9883A’s on-chip PLL generates a pixel clock from the
Hsync input. Pixel clock output frequencies range from 12 MHz to
140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS.
When the COAST signal is presented, the PLL maintains its
output frequency in the absence of Hsync. A sampling phase
adjustment is provided. Data, Hsync, and clock output phase
relationships are maintained. The AD9883A also offers full sync
processing for composite sync and sync-on-green applications.
A clamp signal is generated internally or may be provided by
the user through the CLAMP input pin. This interface is fully
programmable via a 2-wire serial interface.
Fabricated in an advanced CMOS process, the AD9883A is pro-
vided in a space-saving 80-lead LQFP surface-mount plastic package
and is specified over the –40°C to +85°C temperature range.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.