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AD9883AKSTZ-110 参数 Datasheet PDF下载

AD9883AKSTZ-110图片预览
型号: AD9883AKSTZ-110
PDF下载: 下载PDF文件 查看货源
内容描述: 110 MSPS / 140 MSPS模拟接口用于平板显示器 [110 MSPS/140 MSPS Analog Interface for Flat Panel Displays]
分类和应用: 显示器消费电路商用集成电路
文件页数/大小: 28 页 / 223 K
品牌: ADI [ ADI ]
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AD9883A  
Table V. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats  
Refresh Horizontal AD9883AKST AD9883ABST  
Standard  
Resolution  
Rate  
Frequency  
Pixel Rate  
VCORNGE Current VCORNGE Current  
VGA  
640 × 480  
60 Hz  
72 Hz  
75 Hz  
85 Hz  
31.5 kHz  
37.7 kHz  
37.5 kHz  
43.3 kHz  
25.175 MHz  
31.500 MHz  
31.500 MHz  
36.000 MHz  
00  
00  
00  
01  
110  
110  
110  
100  
00  
01  
01  
01  
011  
010  
010  
010  
SVGA  
XGA  
800 × 600  
56 Hz  
60 Hz  
72 Hz  
75 Hz  
85 Hz  
35.1 kHz  
37.9 kHz  
48.1 kHz  
46.9 kHz  
53.7 kHz  
36.000 MHz  
40.000 MHz  
50.000 MHz  
49.500 MHz  
56.250 MHz  
01  
01  
01  
01  
01  
100  
100  
101  
101  
101  
01  
01  
01  
01  
01  
010  
011  
100  
100  
101  
1024 × 768  
60 Hz  
70 Hz  
75 Hz  
80 Hz  
85 Hz  
48.4 kHz  
56.5 kHz  
60.0 kHz  
64.0 kHz  
68.3 kHz  
65.000 MHz  
75.000 MHz  
78.750 MHz  
85.500 MHz  
94.500 MHz  
10  
10  
10  
10  
10  
101  
100  
100  
101  
101  
10  
10  
10  
10  
10  
011  
011  
011  
100  
100  
SXGA  
1280 × 1024 60 Hz  
64.0 kHz  
80.0 kHz  
108.000 MHz  
135.000 MHz  
10  
11  
110  
110  
10  
11  
101  
101  
75 Hz  
Timing  
Three things happen to Horizontal Sync in the AD9883A. First,  
the polarity of Hsync input is determined and will thus have a  
known output polarity. The known output polarity can be pro-  
grammed either active high or active low (register 0EH, Bit 5).  
Second, HSOUT is aligned with DATACK and data outputs.  
Third, the duration of HSOUT (in pixel clocks) is set via regis-  
ter 07H. HSOUT is the sync signal that should be used to drive  
the rest of the display system.  
The following timing diagrams show the operation of the  
AD9883A.  
The output data clock signal is created so that its rising edge  
always occurs between data transitions, and can be used to latch  
the output data externally.  
There is a pipeline in the AD9883A, which must be flushed  
before valid data becomes available. This means four data sets  
are presented before valid data is available.  
Coast Timing  
In most computer systems, the Hsync signal is provided con-  
tinuously on a dedicated wire. In these systems, the COAST  
input and function are unnecessary, and should not be used and  
the pin should be permanently connected to the inactive state.  
tPER  
tCYCLE  
In some systems, however, Hsync is disturbed during the Vertical  
Sync period (Vsync). In some cases, Hsync pulses disappear.  
In other systems, such as those that employ Composite Sync  
(Csync) signals or embedded Sync-on-Green (SOG), Hsync  
includes equalization pulses or other distortions during Vsync. To  
avoid upsetting the clock generator during Vsync, it is impor-  
tant to ignore these distortions. If the pixel clock PLL sees  
extraneous pulses, it will attempt to lock to this new frequency,  
and will have changed frequency by the end of the Vsync period.  
It will then take a few lines of correct Hsync timing to recover  
at the beginning of a new frame, resulting in a “tearing” of the  
image at the top of the display.  
DATACK  
tSKEW  
DATA  
HSOUT  
Figure 7. Output Timing  
Hsync Timing  
Horizontal Sync (Hsync) is processed in the AD9883A to elimi-  
nate ambiguity in the timing of the leading edge with respect to  
the phase-delayed pixel clock and data.  
The COAST input is provided to eliminate this problem. It is  
an asynchronous input that disables the PLL input and allows  
the clock to free-run at its then-current frequency. The PLL can  
free-run for several lines without significant frequency drift.  
The Hsync input is used as a reference to generate the pixel  
sampling clock. The sampling phase can be adjusted, with respect  
to Hsync, through a full 360° in 32 steps via the Phase Adjust  
Register (to optimize the pixel sampling time). Display systems  
use Hsync to align memory and display write cycles, so it is  
important to have a stable timing relationship between Hsync  
output (HSOUT) and data clock (DATACK).  
REV. B  
–13–