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AD9883AKSTZ-110 参数 Datasheet PDF下载

AD9883AKSTZ-110图片预览
型号: AD9883AKSTZ-110
PDF下载: 下载PDF文件 查看货源
内容描述: 110 MSPS / 140 MSPS模拟接口用于平板显示器 [110 MSPS/140 MSPS Analog Interface for Flat Panel Displays]
分类和应用: 显示器消费电路商用集成电路
文件页数/大小: 28 页 / 223 K
品牌: ADI [ ADI ]
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AD9883A  
The PLL characteristics are determined by the loop filter design, by  
the PLL Charge Pump Current, and by the VCO range setting.  
The loop filter design is illustrated in Figure 6. Recommended  
settings of VCO range and charge pump current for VESA  
standard display modes are listed in Table V.  
4. The 5-Bit Phase Adjust Register. The phase of the generated  
sampling clock may be shifted to locate an optimum sampling  
point within a clock cycle. The Phase Adjust Register provides  
32 phase-shift steps of 11.25° each. The Hsync signal with  
an identical phase shift is available through the HSOUT pin.  
The COAST pin is used to allow the PLL to continue to run  
at the same frequency, in the absence of the incoming Hsync  
signal or during disturbances in Hsync (such as equalization  
pulses). This may be used during the vertical sync period, or  
any other time that the Hsync signal is unavailable. The  
polarity of the COAST signal may be set through the Coast  
Polarity Register. Also, the polarity of the Hsync signal  
may be set through the Hsync Polarity Register. If not  
using automatic polarity detection, the Hsync and COAST  
Polarity bits should be set to match the respective polarities  
of the input signals.  
PV  
D
0.082F C  
C
0.0082F  
Z
P
2.7kR  
Z
FILT  
Figure 6. PLL Loop Filter Detail  
Four programmable registers are provided to optimize the per-  
formance of the PLL. These registers are:  
1. The 12-Bit Divisor Register. The input Hsync frequencies  
range from 15 kHz to 110 kHz. The PLL multiplies the  
frequency of the Hsync signal, producing pixel clock  
frequencies in the range of 12 MHz to 110 MHz. The  
Divisor Register controls the exact multiplication factor.  
This register may be set to any value between 221 and 4095.  
(The divide ratio that is actually used is the programmed  
divide ratio plus one.)  
Power Management  
The AD9883A uses the activity detect circuits, the active inter-  
face bits in the serial bus, the active interface override bits, and  
the power-down bit to determine the correct power state. There  
are three power states, full-power, seek mode, and power-down.  
Table IV summarizes how the AD9883A determines what power  
mode to be in and which circuitry is powered on/off in each of  
these modes. The power-down command has priority over the  
automatic circuitry.  
2. The 2-Bit VCO Range Register. To improve the noise  
performance of the AD9883A, the VCO operating frequency  
range is divided into three overlapping regions. The VCO  
Range Register sets this operating range. The frequency  
ranges for the lowest and highest regions are shown in Table II.  
Table IV. Power-Down Mode Descriptions  
Inputs  
Power-  
Sync  
Powered On or  
Comments  
Table II. VCO Frequency Ranges  
Pixel Clock Range (MHz)  
Mode  
Down1  
Detect2  
Full-Power  
Seek Mode  
1
1
1
0
Everything  
PV1 PV0  
AD9883AKST  
AD9883ABST  
Serial Bus, Sync  
Activity Detect, SOG,  
Band Gap Reference  
0
0
1
1
0
1
0
1
12–32  
32–64  
12–30  
30–60  
64–110  
110–140  
60–120  
120–140  
Power-Down  
0
X
Serial Bus, Sync  
Activity Detect, SOG,  
Band Gap Reference  
3. The 3-Bit Charge Pump Current Register. This register  
allows the current that drives the low-pass loop filter to be  
varied. The possible current values are listed in Table III.  
NOTES  
1Power-down is controlled via Bit 1 in serial bus register 0FH.  
2Sync detect is determined by OR-ing Bits 7, 4, and 1 in serial bus register 14H.  
Table III. Charge Pump Current/Control Bits  
Ip2  
Ip1  
Ip0  
Current (A)  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
50  
100  
150  
250  
350  
500  
750  
1500  
–12–  
REV. B