AD9865
FULL-DUPLEX DATA INTERFACE (Tx AND Rx PORT) TIMING SPECIFICATIONS
AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted.
Table 7.
Parameter
Tx PATH INTERFACE (See Figure 53)
Input Nibble Rate (2× Interpolation)
Input Nibble Rate (4× Interpolation)
Tx Data Setup Time (t
DS
)
Tx Data Hold Time (t
DH
)
Rx PATH INTERFACE
(See Figure 54)
Output Nibble Rate
Rx Data Valid Time (t
DV
)
Rx Data Hold Time (t
DH
)
Temp
Full
Full
Full
Full
Full
Full
Full
Test Level
II
II
II
II
II
II
II
Min
20
10
2.5
1.5
10
3
0
Typ
Max
160
100
Unit
MSPS
MSPS
ns
ns
MSPS
ns
ns
160
1
C
LOAD
=5 pF for digital data outputs.
EXPLANATION OF TEST LEVELS
I
II
III
IV
V
VI
100% production tested.
100% production tested at 25°C and guaranteed by design and characterization at specified temperatures.
Sample tested only.
Parameter is guaranteed by design and characterization testing.
Parameter is a typical value only.
100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.
Rev. A | Page 8 of 48
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