AD9865
Power-Up Default Value
MODE = 0 (Half-Duplex) MODE = 1 (Full-Duplex)
Bit
Address Break-
(Hex)1
down
Description
Width
Comments
CONFIG = 0
CONFIG = 1
CONFIG = 0
CONFIG = 1
0x08
(7:0)
Rx Filter Tuning
Cut-off Frequency
8
Refer to Low-Pass Filter
section.
0x80
0x61
0x80
0x80
Tx/Rx PATH GAIN CONTROL
0x09
(6)
Use SPI Rx Gain
Rx Gain Code
1
6
Default setting is for
hardware Rx gain code via
PGA or Tx data port.
0x00
0x7F
0x00
0x7F
0x00
0x7F
0x00
0x7F
(5:0)
0x0A
(6)
Use SPI Tx Gain
Tx Gain Code
1
6
Default setting is for Tx gain
code via SPI control.
(5:0)
Tx AND Rx PGA CONTROL
0x0B
(6)
(5)
(3)
(2)
(1)
PGA Code for Tx
PGA Code for Rx
Force GAIN strobe
Rx Gain on Tx Port
3-Bit RxPGA Port
1
1
1
1
1
0
1
0
0
0
0
0
0
Default setting is RxPGA
control active.
*Tx port with GAIN strobe
(AD9875/AD9876-compatible).
** 3-bit RxPGA gain map
(AD9975-compatible).
1
1
1
0
0
0
0
1*
0
1*
0
1**
Tx DIGITAL FILTER AND INTERFACE
0x0C
(7:6)
Interpolation
Factor
2
1
01
0
00
0
01
0
01
0
Default setting is 2×
interpolation with LPF
response. Data format is
straight binary for half-
duplex and twos
complement for full-duplex
interface.
(4)
Invert
TXEN/TXSYNC
(3)
(2)
(1)
(0)
Tx 5/5 Nibble*
1
1
1
1
N/A
N/A
0
N/A
N/A
0
0
0
0
1
0
0
0
1
LS Nibble First*
TXCLK neg. edge
Twos complement
*Full-duplex only.
0
0
Rx INTERFACE AND ANALOG/DIGITAL LOOPBACK
0x0D
(7)
(6)
(5)
(4)
Analog Loopback
Digital Loopback*
Rx Port 3-State
1
1
1
1
0
0
0
0
0
0
0
0
0
0
Data format is straight
binary for half-duplex and
twos complement for full-
duplex interface.
Analog loopback: ADC Rx
data fed back to TxDAC.
Digital loopback: Tx input
data to Rx output port.
*Full-duplex only.
0
0
N/A
0
N/A
0
Invert
RXEN/RXSYNC
(3)
(2)
(1)
(0)
RX 5/5 Nibble
1
1
1
1
N/A
N/A
0
N/A
N/A
0
0
0
0
1
0
0
0
1
LS Nibble First*
RXCLK neg. edge
Twos complement
0
0
DIGITAL OUTPUT DRIVE STRENGTH, TxDAC OUTPUT, AND REV ID
0x0E
(7)
Low Drive
Strength
1
0
0
0
0
Default setting is for high
drive strength and IAMP
enabled.
(0)
TxDAC Output
REV ID Number
1
4
0
0
0
0
0x0F
(3:0)
0x00
0x00
0x00
0x00
Tx IAMP GAIN AND BIAS CONTROL
0x10
(7)
Select Tx Gain
1
3
3
3
3
Secondary path G1 = 0, 1, 2,
3, 4.
Primary path N = 0, 1, 2, 3, 4.
0x44
0x44
0x44
0x44
(6:4)
(2:0)
(6:4)
(2:0)
G1
N
0x11
0x12
G2
G3
Secondary path stages:
G2 = 0 to 1.50 in 0.25 steps
and G3 = 0 to 6.
0x62
0x01
0x62
0x01
0x62
0x01
0x62
0x01
(6:4)
(2:0)
Stand_Secondary
Stand_Primary
3
3
Standing current of primary
and secondary path.
Rev. A | Page 20 of 48
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