AD9865
SERIAL PORT
Table 10. SPI Register Mapping
Power-Up Default Value
MODE = 0 (Half-Duplex) MODE = 1 (Full-Duplex)
Bit
Address Break-
(Hex)1
down
Description
Width
Comments
CONFIG = 0
CONFIG = 1
CONFIG = 0
CONFIG = 1
SPI PORT CONFIGURATION AND SOFTWARE RESET
0x00
(7)
(6)
(5)
4-Wire SPI
LSB First
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
Default SPI configuration is
3-wire, MSB first.
S/W Reset
POWER CONTROL REGISTERS (via PWR_DWN pin)
0x01
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1*
1
1
1
1
1
1
1
PWR_DWN = 0.
Default setting is for all
blocks powered on.
Clock Syn.
TxDAC/IAMP
Tx Digital
REF
ADC CML
ADC
PGA Bias
RxPGA
0x02
PWR_DWN = 1.
CLK Syn.
TxDAC/IAMP
Tx Digital
REF
Default setting* is for all
functional blocks powered
down except PLL.
*MODE = CONFIG = 1.
ADC CML
ADC
Setting has PLL powered
down with OSCIN input
routed to RXCLK output.
PGA Bias
RxPGA
HALF-DUPLEX POWER CONTROL
0x03
(7:3)
(2)
Tx OFF Delay
Rx _TXEN
5
1
1
1
Default setting is for TXEN
input to control power
on/off of Tx/Rx path.
Tx driver delayed by 31
1/fDATA clock cycles.
0xFF
0xFF
N/A
N/A
(1)
Tx PWRDN
Rx PWRDN
(0)
PLL CLOCK MULTIPLIER/SYNTHESIZER CONTROL
0x04
(5)
Duty Cycle Enable
fADC from PLL
1
1
2
2
0
0
0
0
Default setting is Duty Cycle
Restore disabled, ADC CLK
from OSCIN input, and PLL
multiplier × 2 setting.
(4)
0
0
0
0
(3:2)
(1:0)
PLL Divide-N
00
01
00
10*
00
01
00
01
PLL Multiplier-M
*PLL multiplier × 4 setting.
0x05
0x06
(2)
OSCIN to RXCLK
Invert RXCLK
1
1
1
2
1
1
2
1
1
0
0
0
1*
0
Full-duplex RXCLK normally
at nibble rate.
*Exception on power-up.
(1)
0
0
0
(0)
Disabled RXCLK
CLKOUT2 Divide
CLKOUT2 Invert
CLKOUT2 Disable
CLKOUT1 Divide
CLKOUT1 Invert
CLKOUT1 Disable
0
0
0
0
(7:6)
(5)
01
0
01
0
01
0
01
0
Default setting is CLKOUT2
and CLKOUT1 enabled with
divide-by-2.
*CLKOUT1 and CLKOUT2
disabled.
(4)
0
0
0
1*
01
0
(3:2)
(1)
01
0
01
0
01
0
(0)
0
0
0
1*
Rx PATH CONTROL
0x07
(5)
(4)
(0)
Initiate Offset Cal.
Rx Low Power
Rx Filter ON
1
1
1
0
0
1
0
0
0
1
0
Default setting has LPF ON
and Rx path at nominal
power bias setting.
1*
1
1*
1
*Rx path to low power.
Rev. A | Page 19 of 48
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