AD9856
THEORY OF OPERATION
To gain a general understanding of the functionality of the
AD9856 it is helpful to refer to Figure 21, which displays a
block diagram of the device architecture. The following is a
general description of the device functionality. Later sections
will detail each of the data path building blocks.
Modulation Mode Operation
After passing through the half-band filter stages, the I/Q data
streams are fed to a Cascaded Integrator-Comb (CIC) filter.
This filter is configured as an interpolating filter, which allows
further upsampling rates of any integer value between 2 and 63,
inclusive. The CIC filter, like the half-bands, has a built-in low-
pass characteristic. Again, this provides for suppression of the
spectral images produced by the upsampling process.
The digital quadrature modulator stage following the CIC filters
is used to frequency shift the baseband spectrum of the incom-
ing data stream up to the desired carrier frequency (this process
is known as
upconversion).
The carrier frequency is controlled
numerically by a Direct Digital Synthesizer (DDS). The DDS
uses its internal reference clock (SYSCLK) to generate the
desired carrier frequency with a high degree of precision. The
carrier is applied to the I and Q multipliers in quadrature fash-
ion (90° phase offset) and summed to yield a data stream that
is the modulated carrier. It should be noted at this point that the
incoming data has been converted from an input sample rate
of f
IN
to an output sample rate of SYSCLK (see the block
diagram).
The sampled carrier is ultimately destined to serve as the input
data to the digital-to-analog converter (DAC) integrated on the
AD9856. The DAC output spectrum is distorted due to the
intrinsic zero-order hold effect associated with DAC-generated
signals. This distortion is deterministic, however, and follows
the familiar SIN(x)/x (or SINC) envelope. Since the SINC
distortion is predictable, it is also correctable. Hence, the presence
of the optional Inverse SINC filter preceding the DAC. This is a
FIR filter, which has a transfer function conforming to the inverse
of the SINC response. Thus, when selected, it modifies the incom-
ing data stream so that the SINC distortion, which would other-
wise appear in the DAC output spectrum is virtually eliminated.
As mentioned earlier, the output data is sampled at the rate of
SYSCLK. Since the AD9856 is designed to operate at SYSCLK
frequencies up to 200 MHz, there is the potential difficulty of
trying to provide a stable input clock (REFCLK). Although
stable, high frequency oscillators are available commercially they
tend to be cost prohibitive. To alleviate this problem, the AD9856
has a built-in programmable clock multiplier circuit. This allows
the user to use a relatively low frequency (thus, less expensive)
oscillator to generate the REFCLK signal. The low frequency
REFCLK signal can then be multiplied in frequency by an
integer factor of between 4 and 20, inclusive, to become the
SYSCLK signal.
QUADRATURE
MODULATOR
CIC
FILTER
12
COS
INV SINC
BYPASS
The AD9856 accepts 12-bit data words, which are strobed into
the Data Assembler via an internal clock. The input, TxENABLE,
serves as the “valve” which allows data to be accepted or ig-
nored by the Data Assembler. The user has the option to feed
the 12-bit data words to the AD9856 as single 12-bit words,
dual 6-bit words, or quad 3-bit words. This provides the user
with the flexibility to use fewer interface pins, if so desired.
Furthermore, the incoming data is assumed to be complex, in
that alternating 12-bit words are regarded as the inphase (I) and
quadrature (Q) components of a symbol.
The rate at which the 12-bit words are presented to the AD9856
will be referred to as the Input Sample Rate (f
IN
). It should be
pointed out that f
IN
is not the same as the baseband data rate
provided by the user. As a matter of fact, it is required that the
user’s baseband data be upsampled by at least a factor of two
(2) before being applied to the AD9856 in order to minimize
the frequency-dependent attenuation associated with the CIC
filter stage (detailed in a later section).
The Data Assembler splits the incoming data word pairs into
separate I/Q data streams. The rate at which the I/Q data word
pairs appear at the output of the Data Assembler will be referred
to as the I/Q Sample Rate (f
IQ
). Since two 12-bit input data
words are used to construct the individual I and Q data paths, it
should be apparent that the input sample rate is twice the I/Q
sample rate (i.e., f
IN
= 2
×
f
IQ
).
Once through the Data Assembler, the I/Q data streams are fed
through two half-band filters (half-band filters #1 and #2). The
combination of these two filters results in a factor of four (4)
increase of the sample rate. Thus, at the output of half-band
filter #2, the sample rate is 4
×
f
IQ
. In addition to the sample
rate increase, the half-band filters provide the low-pass filtering
characteristic necessary to suppress the spectral images pro-
duced by the upsampling process. Further upsampling is avail-
able via an optional third half-band filter (half-band filter #3).
When selected, this provides an overall upsampling factor of
eight (8). Thus, if half-band filter #3 is selected, then the sample
rate at its output is 8
×
f
IQ
.
HALF-BAND
FILTER #3
DATA
IN
TxENABLE
DATA
HALF-BAND HALF-BAND
HBF #3
ASSEMBLER FILTER #1
FILTER #2
BYPASS
12
12
12
I
3, 6, 12
12 MUX
R
SET
12
DAC
INV
SINC
12
Q
12
12
HBF #3
BYPASS
MUX
A
OUT
12
12
MUX
SIN
DDS
HBF #3 BYPASS
(F1)
MUX
(F2)
M = 4...20
REFCLK
MULTIPLIER
(M)
(F3)
2
2
MUX
(F5)
2
(F4)
N
N = 2...63
(SYSCLK)
MUX
REFCLK
Figure 21. AD9856 Block Diagram
REV. B
–13–
AD [ ANALOG DEVICES ]
