AD9850
AD9850BRS
Parameter
Temp
Test Level
Min
Typ
Max
Unit
CMOS LOGIC INPUTS (Including CLKIN)
Logic 1 Voltage, 5 V Supply
Logic 1 Voltage, 3.3 V Supply
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
25°C
25°C
25°C
25°C
25°C
25°C
I
3.5
2.4
V
V
V
µA
µA
pF
IV
IV
I
I
V
0.8
12
12
Input Capacitance
3
POWER SUPPLY (AOUT = 1/3 CLKIN)
+VS Current @
62.5 MHz Clock, 3.3 V Supply
110 MHz Clock, 3.3 V Supply
62.5 MHz Clock, 5 V Supply
125 MHz Clock, 5 V Supply
Full
Full
Full
Full
VI
VI
VI
VI
30
47
44
76
48
60
64
96
mA
mA
mA
mA
PDISS
@
62.5 MHz Clock, 3.3 V Supply
110 MHz Clock, 3.3 V Supply
62.5 MHz Clock, 5 V Supply
125 MHz Clock, 5 V Supply
PDISS Power-Down Mode
5 V Supply
Full
Full
Full
Full
VI
VI
VI
VI
100
155
220
380
160
200
320
480
mW
mW
mW
mW
Full
Full
V
V
30
10
mW
mW
3.3 V Supply
*Tested by measuring output duty cycle variation.
Specifications subject to change without notice.
(V = 5 V ؎ 5% except as noted, RSET = 3.9 k⍀)
TIMING CHARACTERISTICS*
S
AD9850BRS
Min Typ Max
Parameter
Temp
Test Level
Unit
tDS (Data Setup Time)
tDH (Data Hold Time)
tWH (W_CLK Minimum Pulse Width High)
tWL (W_CLK Minimum Pulse Width Low)
tWD (W_CLK Delay after FQ_UD)
tCD (CLKIN Delay after FQ_UD)
tFH (FQ_UD High)
Full
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
IV
3.5
3.5
3.5
3.5
7.0
3.5
7.0
7.0
ns
ns
ns
ns
ns
ns
ns
ns
tFL (FQ_UD Low)
tCF (Output Latency from FQ_UD)
Frequency Change
Full
Full
Full
Full
Full
Full
Full
Full
25°C
IV
IV
IV
IV
IV
IV
IV
IV
V
18
13
7.0
3.5
3.5
5
CLKIN Cycles
CLKIN Cycles
ns
ns
Phase Change
tFD (FQ_UD Minimum Delay after W_CLK)
tRH (CLKIN Delay after RESET Rising Edge)
tRL (RESET Falling Edge after CLKIN)
tRS (Minimum RESET Width)
tOL (RESET Output Latency)
tRR (Recovery from RESET)
ns
CLKIN Cycles
CLKIN Cycles
CLKIN Cycles
µs
13
2
Wake-Up Time from Power-Down Mode
5
*Control functions are asynchronous with CLKIN.
Specifications subject to change without notice.
–3–
REV. H
ADI [ ADI ]
