AD9767
INTERLEAVED MODE TIMING
For the following section, refer to Figure 25.
When the mode pin is at Logic 0, the AD9767 operates in inter-
leaved mode. WRT1 now functions as IQWRT and CLK1
functions as IQCLK. WRT2 functions as IQSEL and CLK2
functions as IQRESET.
Data enters the device on the rising edge of IQWRT. The logic
level of IQSEL will steer the data to either Channel Latch 1
(IQSEL = 1) or to Channel Latch 2 (IQSEL = 0).
When IQRESET is high, IQCLK is disabled. When IQRESET
goes low, the following rising edge on IQCLK will update both
DAC latches with the data present at their inputs. In the inter-
leaved mode IQCLK is divided by 2 internally. Following this
first rising edge, the DAC latches will only be updated on every
other rising edge of IQCLK. In this way, IQRESET can be used
to synchronize the routing of the data to the DACs.
As with the dual port mode, IQCLK should occur before or
simultaneously with IQWRT.
INTERLEAVED
DATA IN, PORT 1
PORT 1
INPUT
LATCH
DAC1
LATCH
DAC1
IQWRT
IQSEL
PORT 2
INPUT
LATCH
IQCLK
IQRESET
DEINTERLEAVED
DATA OUT
DAC2
LATCH
DAC2
The digital inputs are CMOS-compatible with logic thresholds,
V
THRESHOLD
, set to approximately half the digital positive supply
(DVDD) or
V
THRESHOLD
= DVDD/2
(± 20%)
The internal digital circuitry of the AD9767 is capable of oper-
ating over a digital supply range of 3 V to 5.5 V. As a result, the
digital inputs can also accommodate TTL levels when DVDD is
set to accommodate the maximum high level voltage of the TTL
drivers V
OH
(MAX). A DVDD of 3 V to 3.3 V will typically
ensure proper compatibility with most TTL logic families. Fig-
ure 28 shows the equivalent digital input circuit for the data and
clock inputs. The sleep mode input is similar with the exception
that it contains an active pull-down circuit, thus ensuring that
the AD9767 remains enabled if this input is left disconnected.
Since the AD9767 is capable of being updated up to 125 MSPS,
the quality of the clock and data input signals are important in
achieving the optimum performance. Operating the AD9767
with reduced logic swings and a corresponding digital supply
(DVDD) will result in the lowest data feedthrough and on-chip
digital noise. The drivers of the digital data interface circuitry
should be specified to meet the minimum setup and hold times
of the AD9767 as well as its required min/max input logic level
thresholds.
Digital signal paths should be kept short and run lengths matched
to avoid propagation delay mismatch. The insertion of a low
value resistor network (i.e., 20
Ω
to 100
Ω)
between the AD9767
digital inputs and driver outputs may be helpful in reducing any
overshooting and ringing at the digital inputs that contribute to
digital feedthrough. For longer board traces and high data up-
date rates, stripline techniques with proper impedance and
termination resistors should be considered to maintain “clean”
digital inputs.
The external clock driver circuitry should provide the AD9767
with a low jitter clock input meeting the min/max logic levels
while providing fast edges. Fast clock edges will help minimize
any jitter that will manifest itself as phase noise on a recon-
structed waveform. Thus, the clock input should be driven by
the fastest logic family suitable for the application.
Note that the clock input could also be driven via a sine wave,
which is centered around the digital threshold (i.e., DVDD/2)
and meets the min/max logic threshold. This will typically result
in a slight degradation in the phase noise, which becomes more
noticeable at higher sampling rates and output frequencies.
Also, at higher sampling rates, the 20% tolerance of the digital
logic threshold should be considered since it will affect the effec-
tive clock duty cycle and, subsequently, cut into the required
data setup and hold times.
DVDD
2
Figure 25. Latch Structure Interleaved Mode
Timing specifications for interleaved mode are given in Figures
26 and 27.
t
S
DATA IN
t
H
IQSEL
t
H
*
IQWRT
t
LPW
IQCLK
IOUTA
OR
IOUTB
t
PD
* Applies to falling edge of IQCLK/IQWRT and IQSEL only
Figure 26. Interleaved Mode Timing
INTERLEAVED
DATA
IQSEL
xx
D1
D2
D3
D4
D5
IQWRT
IQCLK
DIGITAL
INPUT
IQRESET
DAC OUTPUT
PORT 1
DAC OUTPUT
PORT 2
xx
D1
D3
Figure 28. Equivalent Digital Input
xx
D2
D4
Figure 27. Interleaved Mode Timing
–12–
REV. B
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