AD9764AR 参数 Datasheet PDF下载

AD9764

PIN CONFIGURATION

(MSB) DB13 1

DB12 2

DB11 3

DB10 4

DB9 5

DB8 6

28 CLOCK

27 DVDD

26 DCOM

25 NC

AD9764

24 AVDD

TOP VIEW 23 COMP2

DB7 7 (Not to Scale) 22 I

OUTA

DB6 8

DB5 9

DB4 10

DB3 11

DB2 12

DB1 13

DB0 14

21 I

OUTB

20 ACOM

19 COMP1

18 FS ADJ

17 REFIO

16 REFLO

15 SLEEP

NC = NO CONNECT

PIN FUNCTION DESCRIPTIONS

Pin No.

1

2–13

14

15

16

17

Name

DB13

DB12–DB1

DB0

SLEEP

REFLO

REFIO

Description

Most Significant Data Bit (MSB).

Data Bits 1–12.

Least Significant Data Bit (LSB).

Power-Down Control Input. Active High. Contains active pull-down circuit; it may be left unterminated if

not used.

Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference.

Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to

AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM).

Requires 0.1

µF

capacitor to ACOM when internal reference activated.

Full-Scale Current Output Adjust.

Bandwidth/Noise Reduction Node. Add 0.1

µF

to AVDD for optimum performance.

Analog Common.

Complementary DAC Current Output. Full-scale current when all data bits are 0s.

DAC Current Output. Full-scale current when all data bits are 1s.

Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1

µF

capacitor.

Analog Supply Voltage (+2.7 V to +5.5 V).

No Internal Connection.

Digital Common.

Digital Supply Voltage (+2.7 V to +5.5 V).

Clock Input. Data latched on positive edge of clock.

18

19

20

21

22

23

24

25

26

27

28

FS ADJ

COMP1

ACOM

I

OUTB

I

OUTA

COMP2

AVDD

NC

DCOM

DVDD

CLOCK

REV. B

–5–