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AD9761ARS 参数 Datasheet PDF下载

AD9761ARS图片预览
型号: AD9761ARS
PDF下载: 下载PDF文件 查看货源
内容描述: 双10位通道TxDAC + ⑩ 2倍插值滤波器 [Dual 10-Bit TxDAC+⑩ with 2x Interpolation Filters]
分类和应用: 转换器数模转换器光电二极管
文件页数/大小: 23 页 / 249 K
品牌: AD [ ANALOG DEVICES ]
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AD9761
PIN FUNCTION DESCRIPTIONS
Pin No.
1
2–9
10
11
12
13
14
15
16
17
18
19
20
Name
DB9
DB8–DB1
DB0
CLOCK
WRITE
SELECT
DVDD
DCOM
COMP3
QOUTA
QOUTB
REFLO
REFIO
Description
Most Significant Data Bit (MSB).
Data Bits 1-8.
Least Significant Data Bit (LSB).
Clock Input. Both DACs’ outputs updated on positive edge of clock and digital filters read respective
input registers.
Write input. DAC input registers latched on positive edge of write.
Select Input. Select high routes input data to I DAC, select low routes data to Q DAC.
Digital Supply Voltage (+2.7 V to +5.5 V).
Digital Common.
Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1
µF
capacitor.
Q DAC Current Output. Full-scale current when all data bits are 1s.
Q DAC Complementary Current Output. Full-scale current when all data bits are 0s.
Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal
reference.
Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.2 V
reference output when internal reference activated. Requires 0.1
µF
capacitor to ACOM when inter-
nal reference activated.
Full-Scale Current Output Adjust. Resistance to ACOM sets full-scale output current.
Bandwidth/Noise Reduction Node. Add 0.1
µF
to AVDD for optimum performance.
Analog Supply Voltage (+2.7 V to +5.5 V).
Analog Common.
I DAC Complementary Current Output. Full-scale current when all data bits are 0s.
I DAC Current Output. Full-scale current when all data bits are 1s.
Internal Bias Node for Switch Driver Circuitry. Decouple to AGND with 0.1
µF
capacitor.
Power-Down control input if asserted for four clock cycles or longer. Reset control input if asserted
for less than four clock cycles. Active high. Connect to DCOM if not used. Refer to RESET/SLEEP
section.
21
22
23
24
25
26
27
28
FSADJ
COMP2
AVDD
ACOM
IOUTB
IOUTA
COMP1
RESET/SLEEP
PIN CONFIGURATION
(MSB) DB9 1
DB8 2
DB7 3
DB6 4
DB5 5
DB4 6
28 RESET/SLEEP
27 COMP1
26 IOUTA
25 IOUTB
AD9761
24 ACOM
TOP VIEW 23 AVDD
(Not to Scale) 22 COMP2
DB3 7
DB2 8
DB1 9
(LSB) DB0 10
CLOCK 11
WRITE 12
SELECT 13
DVDD 14
21 FSADJ
20 REFIO
19 REFLO
18 QOUTB
17 QOUTA
16 COMP3
15 DCOM
–6–
REV. A