AD9761
DYNAMIC SPECIFICATIONS
Parameter
DYNAMIC PERFORMANCE
Maximum Output Update Rate
Output Settling Time (t
ST
to 0.025%)
Output Propagation Delay (t
PD
)
Glitch Impulse
Output Rise Time (10% to 90%)
Output Fall Time (10% to 90%)
AC LINEARITY TO NYQUIST
Signal-to-Noise and Distortion (SINAD)
f
OUT
= 1 MHz; CLOCK = 40 MSPS
Effective Number of Bits (ENOBs)
Total Harmonic Distortion (THD)
f
OUT
= 1 MHz; CLOCK = 40 MSPS
Spurious-Free Dynamic Range (SFDR)
f
OUT
= 1 MHz; CLOCK = 40 MSPS; 10 MHz Span
Channel Isolation
f
OUT
= 8 MHz; CLOCK = 40 MSPS; 10 MHz Span
(T
MIN
to T
MAX
, AVDD = +5 V, DVDD = +5 V, I
OUTFS
= 10 mA, Differential Transformer Coupled Output,
50 Doubly Terminated, unless otherwise noted)
Min
40
35
55
5
2.5
2.5
Typ
Max
Units
MSPS
ns
Input Clock Cycles
pV-s
ns
ns
56
9.0
59
9.5
–68
–58
dB
Bits
dB
dB
dBC
59
68
90
DIGITAL SPECIFICATIONS
(T
Parameter
MIN
to T
MAX
, AVDD = +5 V, DVDD = +5 V, I
OUTFS
= 10 mA unless otherwise noted)
Min
3.5
2.4
Typ
5
3
0
0
Max
Units
V
V
V
V
µA
µA
pF
ns
ns
ns
ns
ns
DIGITAL INPUTS
Logic “1” Voltage @ DVDD = +5 V
Logic “1” Voltage @ DVDD = +3 V
Logic “0” Voltage @ DVDD = +5 V
Logic “0” Voltage @ DVDD = +3 V
Logic “1” Current
Logic “0” Current
Input Capacitance
Input Setup Time (t
S
)
Input Hold Time (t
H
)
CLOCK High
CLOCK Low
Invalid CLOCK/WRITE Window (t
CINV
)
1
–10
–10
5
3
2
5
5
1
1.3
0.9
+10
+10
5
NOTES
1
t
CINV
is an invalid window of 4 ns duration beginning 1 ns
AFTER
the rising edge of WRITE in which the rising edge of CLOCK
MUST NOT
occur.
Specifications subject to change without notice.
t
S
DB9–DB0
DAC
INPUTS
t
H
"I" DATA
"Q" DATA
SELECT
WRITE
NOTES: WRITE AND CLOCK CAN BE TIED
TOGETHER. FOR TYPICAL EXAMPLES, REFER
TO DIGITAL INPUTS AND INTERLEAVED INTERFACE
CONSIDERATION SECTION.
CLOCK
t
CINV
Figure 1. Timing Diagram
REV. A
–3–
AD [ ANALOG DEVICES ]
