AD9650
Default Default
Address Register
Bit 7
(MSB)
Bit 0
(LSB)
Value
(Hex)
Notes/
Comments
(Hex)
Name
Bit 6
Bit 5
Bit 4
Bit 3
Open
Bit 2
Bit 1
0x0D
Test mode
(local)
Open
Open
ResetPN
long gen
Reset
PN short
gen
Output test mode
000 = off (default)
001 = midscale short
010 = positive FS
011 = negative FS
0x00
When this
register is set,
the test data
is placed on
the output
pins in place of
normal data.
100 = alternating checkerboard
101 = PN long sequence
110 = PN short sequence
111 = one/zero word toggle
0x0E
0x0F
BIST enable
(global)
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Reset BIST Open
sequence
BIST
enable
0x04
ADC input
(global)
Open
Open
Common- 0x00
mode
servo
enable
0x10
0x14
Offset adjust
(local)
Offset adjust in LSBs from +127 to −128
(twos complement format)
0x00
Output
mode
Drive
Output
type
CMOS
output
0 = CMOS interleave
Output
enable
bar
Open
Output
invert
(local)
Output format
00 = offset binary
01 = twos
complement
01 = gray code
11 = offset binary
(local)
0x00
Configures the
outputs and
the format of
the data.
strength
0 = ANSI
LVDS;
(must be
written
low)
(local)
1 = LVDS
(global)
enable
1 =
(global)
reduced
swing
LVDS
(global)
0x16
Clock phase
control
(global)
Invert
DCO
clock
Open
Open
Open
Open
Input clock divider phase adjust
000 = no delay
0x00
Allows
selection of
clock delays
into the input
clock divider.
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
0x17
DCO output
delay (global)
Open
Open
Open
DCO clock delay
(delay = 2500 ps × register value/31)
00000 = 0 ps
0x00
00001 = 81 ps
00010 = 161 ps
…
11110 = 2419 ps
11111 = 2500 ps
0x24
0x25
0x30
BIST signature
LSB (local)
BIST signature[7:0]
0x00
0x00
0x00
Read only.
Read only.
BIST signature
MSB (local)
BIST signature[15:8]
Dither
enable (local)
Open
Open
Open
Open
Open
Open
Dither
enable
Open
Open
Open
Open
Open
Digital Feature Control
0x100
SYNC control
(global)
Open
Clock
divider
next
Clock
divider
SYNC
Master
SYNC
enable
0x00
SYNC
only
enable
Rev. 0 | Page 41 of 44
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