AD9650
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 17 are not currently supported for this device.
Table 17. Memory Map Registers
Address Register
Bit 7
(Hex)
Name
(MSB)
Chip Configuration Registers
0
0x00
SPI port
configuration
(global)
Bit 6
LSB first
Bit 5
Soft reset
Bit 4
1
Bit 3
1
Bit 2
Soft reset
Bit 1
LSB first
Bit 0
(LSB)
0
Default
Value
(Hex)
0x18
Default
Notes/
Comments
The nibbles
are mirrored
so that LSB-
first mode or
MSB-first mode
registers
correctly,
regardless of
shift mode.
Read only.
Speed grade
ID used to
differentiate
devices; read
only.
0x03
Bits are set
to determine
which device
on the chip
receives the
next write
command;
applies to local
registers only.
Synchronously
transfers data
from the
master shift
register to the
slave.
Determines
various generic
modes of chip
operation.
0x01
0x02
Chip ID
(global)
Chip grade
(global)
Open
8-bit Chip ID[7:0]
(AD9650 = 0x32, default)
Speed grade ID
Open
Open
001 = 105 MSPS
010 = 80 MSPS
011 = 65 MSPS
100 = 25 MSPS
Open
Open
Open
Open
Open
0x32
Open
Open
Channel Index and Transfer Registers
0x05
Channel
Open
index
Data
Channel
B
(default)
Data
Channel
A
(default)
0xFF
Transfer
Open
Open
Open
Open
Open
Open
Open
Transfer
0x00
ADC Functions
0x08
Power
modes (local)
1
Open
External
power-
down pin
function
(local)
0 = pdwn
1 = stndby
Open
Open
0x09
Global clock
(global)
Open
Open
Open
Open
Open
0x0B
Clock divide
(global)
Open
Open
Open
Open
Open
Internal power-
down mode (local)
00 = normal
operation
01 = full power-
down
10 = standby
11 = normal
operation
Open
Open
Duty
cycle
stabilizer
(default)
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
Open
0x80
0x01
0x00
Clock divide
values other
than 000
automatically
cause the duty
cycle stabilizer
to become
active.
Rev. 0 | Page 40 of 44
AD [ ANALOG DEVICES ]
