AD9513
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
THE EXPOSED PADDLE
IS AN ELECTRICAL AND
THERMAL CONNECTION
VS
CLK
1
2
3
4
5
6
7
8
24 VS
23 OUT1
22 OUT1B
21 VS
25
24
32
1
CLKB
VS
AD9513
TOP VIEW
SYNCB
VREF
S10
20 VS
(Not to Scale)
EXPOSED PAD
(BOTTOM VIEW)
GND
19 OUT2
18 OUT2B
17 VS
S9
17
16
8
9
Figure 5. 32-Lead LFCSP Pin Configuration
Figure 6. Exposed Paddle
Note that the exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to
function properly, the paddle must be soldered to a PCB land that functions as both a heat dissipation path as well as an electrical
ground.
Table 9. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 4 ,17 ,20, 21,
24, 26, 29, 30
VS
Power Supply (3.3 V).
2
CLK
Clock Input.
3
CLKB
Complementary Clock Input.
5
6
SYNCB
VREF
Used to Synchronize Outputs.
Provides 2/3 VS for use as one of the four logic levels on S0 to S10.
7 to16, 25
S10 to S1, S0
Setup Select Pins. These are 4-state logic. The logic levels are VS, GND, 1/3 VS, and 2/3 VS. The
VREF pin provides 2/3 VS. Each pin is internally biased to 1/3 VS so that a pin requiring that logic
level should be left NC (no connection).
18
19
22
23
27
28
31
32
OUT2B
OUT2
OUT1B
OUT1
OUT0B
OUT0
GND
Complementary LVDS/Inverted CMOS Output.
LVDS/CMOS Output.
Complementary LVDS/Inverted CMOS Output. OUT6 includes a delay block.
LVDS/CMOS Output. OUT6 includes a delay block.
Complementary LVDS/Inverted CMOS Output. OUT5 includes a delay block.
LVDS/CMOS Output. OUT5 includes a delay block.
Ground. The exposed paddle on the back of the chip is also GND.
Current Set Resistor to Ground. Nominal value = 4.12 kΩ.
RSET
Rev. 0 | Page 12 of 28
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