AD9510
SPECIFICATIONS
Typical (typ) is given for V
S
= 3.3 V ± 5%; V
S
≤ VCP
S
≤ 5.5 V, T
A
= 25°C, R
SET
= 4.12 kΩ, CPR
SET
= 5.1 kΩ, unless otherwise noted.
Minimum (min) and maximum (max) values are given over full V
S
and T
A
(−40°C to +85°C) variation.
PLL CHARACTERISTICS
Table 1.
Parameter
REFERENCE INPUTS (REFIN)
Input Frequency
Input Sensitivity
Self-Bias Voltage, REFIN
Self-Bias Voltage, REFINB
Input Resistance, REFIN
Input Resistance, REFINB
Input Capacitance
PHASE/FREQUENCY DETECTOR (PFD)
PFD Input Frequency
PFD Input Frequency
PFD Input Frequency
Antibacklash Pulse Width
Antibacklash Pulse Width
Antibacklash Pulse Width
CHARGE PUMP (CP)
I
CP
Sink/Source
High Value
Low Value
Absolute Accuracy
CPR
SET
Range
I
CP
Three-State Leakage
Sink-and-Source Current Matching
I
CP
vs. V
CP
I
CP
vs. Temperature
RF CHARACTERISTICS (CLK2)
Input Frequency
Min
0
1.45
1.40
4.0
4.5
150
1.60
1.50
4.9
5.4
2
Typ
Max
250
1.75
1.60
5.8
6.3
Unit
MHz
mV p-p
V
V
kΩ
kΩ
pF
MHz
MHz
MHz
ns
ns
ns
Test Conditions/Comments
Self-bias voltage of REFIN
1
.
Self-bias voltage of REFINB
1
.
Self-biased
.
Self-biased
.
100
100
45
1.3
2.9
6.0
Antibacklash pulse width 0Dh<1:0> = 00b.
Antibacklash pulse width 0Dh<1:0> = 01b.
Antibacklash pulse width 0Dh<1:0> = 10b.
0Dh<1:0> = 00b (this is the default setting).
0Dh<1:0> = 01b.
0Dh<1:0> = 10b.
Programmable.
With CPR
SET
= 5.1 kΩ.
V
CP
= VCPs/2.
4.8
0.60
2.5
2.7/10
1
2
1.5
2
1.6
mA
mA
%
kΩ
nA
%
%
%
GHz
0.5 < V
CP
< VCPs − 0.5 V.
0.5 < V
CP
< VCPs − 0.5 V.
V
CP
= VCPs/2 V.
Frequencies > 1200 MHz (LVPECL) or 800 MHz
(LVDS) require a minimum divide-by-2 (see the
Self-biased; enables ac coupling.
With 200 mV p-p signal applied.
CLK2 ac-coupled; CLK2B capacitively
bypassed to RF ground.
Self-biased.
Difference at PFD.
See the VCO/VCXO Feedback Divider—N (P, A, B)
section.
Input Sensitivity
Input Common-Mode Voltage, V
CM
Input Common-Mode Range, V
CMR
Input Sensitivity, Single-Ended
Input Resistance
Input Capacitance
CLK2 VS. REFIN DELAY
PRESCALER (PART OF N DIVIDER)
Prescaler Input Frequency
P = 2 DM (2/3)
P = 4 DM (4/5)
P = 8 DM (8/9)
P = 16 DM (16/17)
P = 32 DM (32/33)
CLK2 Input Frequency for PLL
1.5
1.3
150
1.6
150
1.7
1.8
mV p-p
V
V
mV p-p
kΩ
pF
ps
4.0
4.8
2
500
5.6
600
1000
1600
1600
1600
300
MHz
MHz
MHz
MHz
MHz
MHz
A, B counter input frequency.
Rev. A | Page 4 of 60
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