AD9510
FUNCTION PIN
DISTRIBUTION SECTION
The FUNCTION pin (16) has three functions that are selected
by the value in Register 58h<6:5>. This pin is internally pulled
down by a 30 kΩ resistor. If this pin is left NC, the part is in
reset by default. To avoid this, connect this pin to VS with a
1 kΩ resistor.
As previously mentioned, the AD9510 is partitioned into two
operational sections: PLL and distribution. The PLL Section
was discussed previously. If desired, the distribution section can
be used separately from the PLL section.
CLK1 AND CLK2 CLOCK INPUTS
RESETB: 58h<6:5> = 00b (Default)
Either CLK1 or CLK2 may be selected as the input to the
distribution section. The CLK1 input can be connected to drive
the distribution section only. CLK1 is selected as the source for
the distribution section by setting Register 45h<0> = 1. This is
the power-up default state.
In its default mode, the FUNCTION pin acts as RESETB, which
generates an asynchronous reset or hard reset when pulled low.
The resulting reset writes the default values into the serial
control port buffer registers as well as loading them into the
chip control registers. When the RESETB signal goes high
again, a synchronous sync is issued (see the SYNCB: 58h<6:5>
= 01b section) and the AD9510 resumes operation according to
the default values of the registers.
CLK1 and CLK2 work for inputs up to 1600 MHz. The jitter
performance is improved by a higher input slew rate. The input
level should be between approximately 150 mV p-p to no more
than 2 V p-p. Anything greater may result in turning on the
protection diodes on the input pins, which could degrade the
jitter performance.
SYNCB: 58h<6:5> = 01b
The FUNCTION pin may be used to cause a synchronization
or alignment of phase among the various clock outputs. The
synchronization applies only to clock outputs that
See Figure 35 for the CLK1 and CLK2 equivalent input circuit.
These inputs are fully differential and self-biased. The signal
should be ac-coupled using capacitors. If a single-ended input
must be used, this can be accommodated by ac coupling to one
side of the differential input only. The other side of the input
should be bypassed to a quiet ac ground by a capacitor.
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are not powered down
the divider is not masked (no sync = 0b)
are not bypassed (bypass = 0b)
The unselected clock input (CLK1 or CLK2) should be powered
down to eliminate any possibility of unwanted crosstalk
between the selected clock input and the unselected clock input.
SYNCB is level and rising edge sensitive. When SYNCB is low,
the set of affected outputs are held in a predetermined state,
defined by each divider’s start high bit. On a rising edge, the
dividers begin after a predefined number of fast clock cycles
(fast clock is the selected clock input, CLK1 or CLK2) as
determined by the values in the divider’s phase offset bits.
DIVIDERS
Each of the eight clock outputs of the AD9510 has its own
divider. The divider can be bypassed to get an output at the
same frequency as the input (1×). When a divider is bypassed,
it is powered down to save power.
The SYNCB application of the FUNCTION pin is always active,
regardless of whether the pin is also assigned to perform reset
or power-down. When the SYNCB function is selected, the
FUNCTION pin does not act as either RESETB or PDB.
All integer divide ratios from 1 to 32 may be selected. A divide
ratio of 1 is selected by bypassing the divider.
PDB: 58h<6:5> = 11b
Each divider can be configured for divide ratio, phase, and duty
cycle. The phase and duty cycle values that can be selected
depend on the divide ratio that is chosen.
The FUNCTION pin may also be programmed to work as an
asynchronous full power-down, PDB. Even in this full power-
down mode, there is still some residual VS current because
some on-chip references continue to operate. In PDB mode,
the FUNCTION pin is active low. The chip remains in a power-
down state until PDB is returned to logic high. The chip returns
to the settings programmed prior to the power-down.
See the Chip Power-Down or Sleep Mode—PDB section for
more details on what occurs during a PDB initiated power-
down.
Rev. A | Page 33 of 60
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