AD9280
EXTERNAL REFERENCE OPERATION
Using an external reference may provide more flexibility and
improve drift and accuracy. Figures 21 through 23 show ex-
amples of how to use an external reference with the AD9280.
To use an external reference, the user must disable the internal
reference amplifier by connecting the REFSENSE pin to VDD.
The user then has the option of driving the VREF pin, or driv-
ing the REFTS and REFBS pins.
The AD9280 contains an internal reference buffer (A2), that
simplifies the drive requirements of an external reference. The
external reference must simply be able to drive a 10 kΩ load.
Figure 21 shows an example of the user driving the top and bottom
references. REFTS is connected to a low impedance 2 V source
and REFBS is connected to a low impedance 1 V source. REFTS
and REFBS may be driven to any voltage within the supply as long
as the difference between them is between 1 V and 2 V.
2V
1V
10k
REFTS
REFBS
10k
REF
SENSE
AVDD
MODE
10k
REFBF
10k
A2
A/D
CORE
4.2k
TOTAL
0.1 F
10 F
AIN
SHA
Figure 23a shows an example of the external references driving
the REFTF and REFBF pins that is compatible with the
AD876. REFTS is shorted to REFTF and driven by an external
4 V low impedance source. REFBS is shorted to REFBF and
driven by a 2 V source. The MODE pin is connected to GND
in this configuration.
4V
VIN
2V
4V
10 F
2V
0.1 F
0.1 F
0.1 F
REFTS
REFTF
AD9280
REFBF
REFBS
VREF
AVDD
REFSENSE
MODE
AD9280
Figure 23a. External Reference—2 V p-p Input Span
REFTF
0.1 F
2V
1V
REFTS
+5V
6
REFT
5
8
7
C3
0.1 F
C2
10 F
C5
0.1 F
6
REFB
3
4
C1
0.1 F
REFBF
C6
0.1 F
C4
0.1 F
REFTF
0.1 F
AD9280
REFBS
2
Figure 21. External Reference Mode—1 V p-p Input Span
Figure 22 shows an example of an external reference generating
2.5 V at the shorted REFTS and REFBS inputs. In this in-
stance, a REF43 2.5 V reference drives REFTS and REFBS. A
resistive divider generates a 1 V VREF signal that is buffered by
A3. A3 must be able to drive a 10 kΩ, capacitive load. Choose
this op amp based on noise and accuracy requirements.
Figure 23b. Kelvin Connected Reference Using the AD9280
STANDBY OPERATION
3.0V
2.5V
2.0V
AD9280
AIN
REFTS
REFBS
0.1 F
REFTF
VREF
1.0 F
0.1 F
0.1 F
REFBF
AVDD/2
+5V
AVDD
MODE
REFSENSE
0.1 F
10 F
AVDD
AVDD
The ADC may be placed into a powered down (sleep) mode by
driving the STBY (standby) pin to logic high potential and
holding the clock at logic low. In this mode the typical power
drain is approximately 4 mW.
The ADC will “wake up” in 400 ns (typ) after the standby pulse
goes low.
CLAMP OPERATION
10 F
1.5k
A3
0.1 F
0.1 F
1k
REF43
0.1 F
Figure 22. External Reference Mode—1 V p-p Input
Span 2.5 V
CM
The AD9280ARS features an optional clamp circuit for dc
restoration of video or ac coupled signals. Figure 24 shows the
internal clamp circuitry and the external control signals needed
for clamp operation. To enable the clamp, apply a logic high to
the CLAMP pin. This will close the switch SW1. The clamp
amplifier will then servo the voltage at the AIN pin to be equal
to the clamp voltage applied at the CLAMPIN pin. After the
desired clamp level is attained, SW1 is opened by taking
CLAMP back to a logic low. Ignoring the droop caused by the
input bias current, the input capacitor CIN will hold the dc
voltage at AIN constant until the next clamp interval. The input
resistor RIN has a minimum recommended value of 10
Ω,
to
maintain the closed-loop stability of the clamp amplifier.
–12–
REV. D
AD [ ANALOG DEVICES ]
