AD9200
Parameter
DIGITAL INPUTS
High Input Voltage
Low Input Voltage
DIGITAL OUTPUTS
High-Z Leakage
Data Valid Delay
Data Enable Delay
Data High-Z Delay
LOGIC OUTPUT (with DRVDD = 3 V)
High Level Output Voltage (I
OH
= 50
µA)
High Level Output Voltage (I
OH
= 0.5 mA)
Low Level Output Voltage (I
OL
= 1.6 mA)
Low Level Output Voltage (I
OL
= 50
µA)
LOGIC OUTPUT (with DRVDD = 5 V)
High Level Output Voltage (I
OH
= 50
µA)
High Level Output Voltage (I
OH
= 0.5 mA)
Low Level Output Voltage (I
OL
= 1.6 mA)
Low Level Output Voltage (I
OL
= 50
µA)
CLOCKING
Clock Pulsewidth High
Clock Pulsewidth Low
Pipeline Latency
CLAMP
2
Clamp Error Voltage
Clamp Pulsewidth
NOTES
1
See Figures 1a and 1b.
2
Available only in AD9200ARS and AD9200KST.
Specifications subject to change without notice.
Symbol
V
IH
V
IL
I
OZ
t
OD
t
DEN
t
DHZ
V
OH
V
OH
V
OL
V
OL
V
OH
V
OH
V
OL
V
OL
t
CH
t
CL
Min
2.4
Typ
Max
Units
V
V
µA
ns
ns
ns
V
V
V
V
V
V
V
V
ns
ns
Cycles
Condition
0.3
–10
25
25
13
+2.95
+2.80
+0.4
+0.05
+4.5
+2.4
+0.4
+0.1
22.5
22.5
3
+10
Output = GND to VDD
C
L
= 20 pF
E
OC
t
CPW
±
20
2
±
40
mV
µs
CLAMPIN = 0.5 V–2.7 V, R
IN
= 10
Ω
C
IN
= 1
µF
(Period = 63.5
µs)
10k
REFTS
10k
REFTS
AD9200
REFTF
REFBF
0.4
V
DD
REFBS
MODE
AD9200
4.2k
REFBS
AV
DD
MODE
Figure 1a.
Figure 1b.
REV. E
–3–
AD [ ANALOG DEVICES ]
