AD9200
The actual reference voltages used by the internal circuitry of
the AD9200 appear on REFTF and REFBF. For proper opera-
tion, it is necessary to add a capacitor network to decouple these
pins. The REFTF and REFBF should be decoupled for all
internal and external configurations as shown in Figure 17.
Figure 19 shows the single-ended configuration for 2 V p-p
operation. REFSENSE is connected to GND, resulting in a 2 V
reference output.
2V
0V
REFTF
10 F
0.1 F
AIN
SHA
10k
REFTS
REFBS
10k
10k
10k
A2
A/D
CORE
AD9200
MODE
AVDD
0.1 F
REFTF
AD9200
REFBF
0.1 F
0.1 F
4.2k
TOTAL
0.1 F
10 F
0.1 F
REFBF
Figure 17. Reference Decoupling Network
Note: REFTF = reference top, force
REFBF = reference bottom, force
REFTS = reference top, sense
REFBS = reference bottom, sense
INTERNAL REFERENCE OPERATION
VREF
1.0 F
0.1 F
REF
SENSE
A1
1V
Figures 18, 19 and 20 show example hookups of the AD9200
internal reference in its most common configurations. (Figures
18 and 19 illustrate top/bottom mode while Figure 20 illustrates
center span mode). Figure 29 shows how to connect the AD9200
for 1 V p-p differential operation. Shorting the VREF pin
directly to the REFSENSE pin places the internal reference
amplifier, A1, in unity-gain mode and the resultant reference
output is 1 V. In Figure 18 REFBS is grounded to give an input
range from 0 V to 1 V. These modes can be chosen when the
supply is either +3 V or +5 V. The VREF pin must be bypassed to
AVSS (analog ground) with a 1.0
µF
tantalum capacitor in
parallel with a low inductance, low ESR, 0.1
µF
ceramic capacitor.
1V
0V
10k
REFTS
REFBS
10k
10k
REFBF
VREF
1.0 F
REF
0.1 F
SENSE
A1
1V
10k
A2
AIN
SHA
Figure 19. Internal Reference, 2 V p-p Input Span
(Top/Bottom Mode)
Figure 20 shows the single-ended configuration that gives the
good high frequency dynamic performance (SINAD, SFDR).
To optimize dynamic performance, center the common-mode
voltage of the analog input at approximately 1.5 V. Connect the
shorted REFTS and REFBS inputs to a low impedance 1.5 V
source. In this configuration, the MODE pin is driven to a volt-
age at midsupply (AVDD/2).
Maximum reference drive is 1 mA. An external buffer is re-
quired for heavier loads.
AD9200
MODE
AVDD
0.1 F
2V
1V
AIN
SHA
10k
REFTS
10k
A2
AD9200
MODE
AVDD/2
0.1 F
REFTF
REFTF
A/D
CORE
4.2k
TOTAL
0.1 F
10 F
+1.5V
REFBS
A/D
CORE
4.2k
TOTAL
0.1 F
10 F
0.1 F
10k
10k
REFBF
VREF
1.0 F
0.1 F
REF
SENSE
A1
1V
0.1 F
Figure 18. Internal Reference 1 V p-p Input Span
(Top/Bottom Mode)
Figure 20. Internal Reference 1 V p-p Input Span,
(Center Span Mode)
REV. E
–11–
AD [ ANALOG DEVICES ]
