AD8842
5µs
100
90
5µs
100
90
5V
10
0%
10
0%
2V
5µs
5µS
2V
5µs
Figure 13. Pulse Response—Upper Trace V
IN
@ 2 V/Div
Lower Trace V
OUT
@2 V/Div
Figure 16. Settling Time—Upper Trace LD @ 5 V/Div,
Lower Trace V
OUT
@ 2 V/Div
5V 5µs
100
90
5µs
100
90
10mV
10
0%
10
0%
50mV
2V
500ns
5µS
50ns
Figure 14. Worst Case 1 LSB Step Change Code 80
H
to 7F
H
,
Upper Trace LD @ 5 V/Div, Lower Trace V
OUT
@ 50 mV/Div
Figure 17. Digital Feedthrough—V
OUT
@ 10 mV/Div,
V
IN
= 0 V; Code 7F
H
to 80
H
5µs
5V
100
90
5µs
100
90
10
0%
10
0%
5mV
2V
50ns
5µS
5mV
2µs
Figure 15. Crosstalk—V
OUT
@ 5 mV/Div
Figure 18. Clock Feedthrough—V
OUT
@ 5 mV/Div
REV. 0
–7–