AD876
DIGITAL SPECIFICATIONS
Parameter
LOGIC INPUT
High Level Input Voltage
(T
MIN
to T
MAX
with AV
DD
= +5.0 V, DV
DD
= +5.0 V, DRV
DD
= +3.3 V, V
REFT
= +4.0 V, V
REFB
= +2.0 V,
f
CLOCK
= 20 MSPS, C
L
= 20 pF unless otherwise noted)
Symbol
V
IH
V
IL
I
IH
I
IL
I
IL
C
IN
V
OH
3.0
5.0
5.0
V
OL
3.6
5.25
5.25
C
OUT
I
OZ
5
–10
10
0.7
1.05
0.4
V
V
V
pF
µA
2.4
3.8
2.4
V
V
V
DRV
DD
3.0
5.0
5.25
3.0
5.0
5.25
5.0
5.0
5.0
Min
2.4
4.0
4.2
0.6
1.0
1.05
+10
+50
+10
5
AD876
Typ
Max
Units
V
V
V
V
V
V
µA
µA
µA
pF
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Low Level Input Current (CLK Only)
Input Capacitance
LOGIC OUTPUTS
High Level Output Voltage
(I
OH
= 50
µA)
(I
OH
= 0.5 mA)
Low Level Output Voltage
(I
OL
= 50
µA)
(I
OL
= 0.6 mA)
Output Capacitance
Output Leakage Current
Specifications subject to change without notice.
–10
–50
–10
TIMING SPECIFICATIONS
Symbol
Maximum Conversion Rate
1
Clock Period
Clock High
Clock Low
Output Delay
Pipeline Delay (Latency)
Aperture Delay Time
Aperture Jitter
t
C
t
CH
t
CL
t
OD
Min
20
23
23
10
50
25
25
20
3.5
4
22
Typ
Max
Units
MHz
ns
ns
ns
ns
Clock Cycles
ns
ps
NOTE
1
Conversion rate is operational down to 10 kHz without degradation in specified performance.
SAMPLE N
AIN
SAMPLE N+1
SAMPLE N+2
t
CH
t
CL
CLK
t
C
OUT
DATA N-4
DATA N-3
DATA N-2
DATA N-1
t
OD
DATA N
Figure 1. Timing Diagram
REV. B
–3–
AD [ ANALOG DEVICES ]
