AD8551/AD8552/AD8554
Figure 62 shows the low-side monitor equivalent. In this circuit,
the input common-mode voltage to the AD8552 will be at or near
ground. Again, a 0.1 Ω resistor provides a voltage drop propor-
tional to the return current. The output voltage is given as:
SPICE Model
The SPICE macro-model for the AD855x amplifier is given in
Listing 1. This model simulates the typical specifications for the
AD855x, and it can be downloaded from the Analog Devices
website at http://www.analog.com. The schematic of the
macro-model is shown in Figure 63.
R2
R1
VOUT =V + −
× RSENSE × IL
(24)
Transistors M1 through M4 simulate the rail-to-rail input differ-
ential pairs in the AD855x amplifier. The EOS voltage source in
series with the noninverting input establishes not only the 1 µV
offset voltage, but is also used to establish common-mode and
power supply rejection ratios and input voltage noise. The dif-
ferential voltages from nodes 14 to 16 and nodes 17 to 18 are
reflected to E1, which is used to simulate a secondary pole-zero
combination in the open-loop gain of the amplifier.
For the component values shown in Figure 62, the output trans-
fer function decreases from V+ at –2.5 V/A.
R
0.1⍀
SENSE
I
L
+3V
V+
+3V
8
0.1F
R
100⍀
1
3
2
The voltage at node 32 is then reflected to G1, which adds an
additional gain stage and, in conjunction with CF, establishes
the slew rate of the model at 0.5 V/µs. M5 and M6 are in a
common-source configuration, similar to the output stage of the
AD855x amplifier. EG1 and EG2 fix the quiescent current in
these two transistors at 100 µA, and also help accurately simu-
late the VOUT vs. IOUT characteristic of the amplifier.
1
1/2
AD8552
4
S
G
M1
Si9433
D
MONITOR
OUTPUT
R
2
2.49k⍀
The network around ECM1 creates the common-mode voltage
error, with CCM1 setting the corner frequency for the CMRR
roll-off. The power supply rejection error is created by the
network around EPS1, with CPS3 establishing the corner fre-
quency for the PSRR roll-off. The two current loops around
nodes 80 and 81 are used to create a 42 nV/√Hz noise figure
across RN2. All three of these error sources are reflected to the
input of the op amp model through EOS. Finally, GSY is used
to accurately model the supply current versus supply voltage in-
crease in the AD855x.
Figure 61. A High-Side Load Current Monitor
V+
R
2
2.49k⍀
V
OUT
Q1
V+
This macro-model has been designed to accurately simulate a
number of specifications exhibited by the AD855x amplifier,
and is one of the most true-to-life macro-models available for
any op amp. It is optimized for operation at +27°C. Although
the model will function at different temperatures, it may lose
accuracy with respect to the actual behavior of the AD855x.
R
100⍀
1
1/2 AD8552
0.1⍀
RETURN TO
GROUND
R
SENSE
Figure 62. A Low-Side Load Current Monitor
Precision Voltage Comparator
The AD855x can be operated open-loop and used as a precision
comparator. The AD855x has less than 50 µV of offset voltage
when run in this configuration. The slight increase of offset
voltage stems from the fact that the autocorrection architecture
operates with lowest offset in a closed loop configuration, that
is, one with negative feedback. With 50 mV of overdrive, the de-
vice has a propagation delay of 15 µs on the rising edge and
8 µs on the falling edge.
Care should be taken to ensure the maximum differential volt-
age of the device is not exceeded. For more information, please
refer to the section on Input Overvoltage Protection.
REV. 0
–17–
ADI [ ADI ]
