AD8367
–1.2
–1.3
–1.4
–1.5
–1.6
–1.7
–1.8
–1.9
–2.0
–2.1
–2.2
In some cases, it may be found that, if driven into AGC over-
load, the AD8367 will require unusually long times to recover;
that is, the voltage at DETO will remain at an abnormally high
value and the gain will be at its lowest value. To avoid this situa-
tion, it is recommended that a clamp be placed on the DETO
pin as shown in Figure 11.
1
2
3
4
5
6
7
14
13
12
11
10
9
AD8367
+V
S
MODE
GAIN
DETO
ICOM
V
AGC
RB
Q1
2N2907
0.5V
RA
–50
–40
–30
–20
–10
0
10
8
PIN – dBm (re 200⍀)
C
AGC
0.1F
Figure 9. Leveling Accuracy of the AGC Function
Figure 11. External Clamp to Prevent AGC Overload.
The resistive divider network, RA and RB, should be
designed such that the base of Q1 is driven to 0.5 V.
1.0
V
AGC
0.8
0.6
Modifying the AGC Set Point
If an AGC set point other than the internal one is desired, an
external detector may be used. Figure 12 depicts a method that uses
an external true-rms detector and error integrator to operate the
AD8367 as a closed-loop AGC system with a user-settable
operating level.
0.4
0.2
V
OUT
0
The AD8361 (U2) produces a dc output level which is proportional
to the rms value of its input, taken as a sample of the AD8367 (U1)
output. This dc voltage is compared to an externally-supplied set-
point voltage, and the difference is integrated by the AD820 (U3)
to form the gain control voltage which is applied to the GAIN
input of the AD8367 through the divider composed of R4 and R5.
This divider is included in order to minimize overload recovery
time of the loop by having the integrator saturate at a point that
only slightly overdrives the gain control input of the AD8367. The
scale factor at VAGC is influenced by the values of R4 and R5; for
the values shown, the factor is 86 mV/dB. Note that in this circuit
the AD8367’s MODE pin must be pulled high to obtain correct
feedback polarity because the integrator inverts the polarity of the
feedback signal.
–0.2
–0.4
–0.6
0
5
10
15
20
TIME – s
25
30
35
40
Figure 10. AGC Response to a 32 dB Step in Input
Level (f ꢀ 50 MHz)
It is important to understand that RAGC does not act as if in shunt
with CAGC. Rather, the error-correction process is that of a true
integrator, to guarantee an output that is exactly equal in rms
amplitude to the specified set-point. For large changes in input
level, the integrating action of this loop will be most apparent.
The slew rate of VAGC is determined by the peak output current
from the detector and the capacitor. Thus, for a representative
value of CAGC ꢀ 3 nF, this rate is about 20 V rms or 10 dB/ꢁs,
while the small-signal bandwidth is 1 kHz.
The relationship between set-point voltage and the rms output
voltage of the AD8367 is as follows:
(R1+ 225)
225× 7.5
VOUT −RMS = VSET
×
(6)
Most AGC loops incorporating a true error-integrating technique
have a common weakness. When driven from an increasingly
larger signal, the AGC bias increases to reduce the gain. But
eventually, the gain will fall to its minimum value, for which
further increase in this bias will have no effect on the gain. That
is, the voltage on the loop capacitor will be forced progressively
higher because the detector output is a current, and the AGC
bias is its integral. Consequently there will always be a precipi-
tous increase in this bias voltage when the input to the AD8367
exceeds that value which overdrives the detector, and because
the minimum gain is –2.5 dB, that will happen for all inputs
+2.5 dB greater than the set-point of ~350 mV rms. If possible,
the user should ensure that this limitation is preserved, prefer-
ably with a guard-band of 5 dB to 10 dB below overload.
where 225 is the input resistance of the AD8361 and 7.5 is its
conversion gain. For R1 ꢀ 200 Ω, this reduces to VOUT –RMS
SET ꢆ 0.25.
ꢀ
V
Capacitor C2 sets the averaging time for the rms detector. This
should be made long enough to provide sufficient smoothing of the
detector’s output in the presence of the modulation on the RF
signal. A level fluctuation of less than 1 dB (<5% to 10%) p-p at the
AD8361’s output is a reasonable value. A considerably longer
time-constant will needlessly lower the AGC bandwidth, while a
short time-constant can degrade the accuracy of the true-rms
measurement process. Components C1, R2, and R3 set the control
loop’s bandwidth and stability. The maximum stable loop bandwidth
will be limited by the rms detector’s averaging time constant as
discussed above.
REV. 0
–13–
ADI [ ADI ]
