AD8362
90
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
6
4
60
120
POWER-
DOWN
PIN
2V/DIV
2
0
150
30
+2dBm
VOUT
–2
–4
–6
–8
–10
–12
–14
–10dBm
–20dBm
180
0
0.5V/DIV
–30dBm
210
330
240
300
0
2
4
6
8
10
TIME (µs)
12
14
16
18
20
270
Figure 32. Output Response Using Power-Down Mode for Various RF Input
Levels, Carrier Frequency 900 MHz, CLPF = 0
Figure 35. Input Impedance, ZO = 50 Ω, Differential Drive
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
6
5
0
4
2V/DIV
2
0
–5
+2dBm
–2
–4
–6
–8
–10
–12
–14
–10
–15
–20
–25
–30
–10dBm
–20dBm
–30dBm
0.5V/DIV
0
2
4
6
8
10
12
14
16
18
20
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TIME (ms)
TEMPERATURE (°C)
Figure 33. Output Response Using Power-Down Mode for Various RF Input
Levels, Carrier Frequency 900 MHz, CLPF = 0.1 µF
Figure 36. Change in VREF vs. Temperature, 3 Sigma to Either Side of Mean
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0
6
300
250
200
150
100
50
4
2V/DIV
VPOS
2
0
–2
–4
–6
–8
–10
–12
–14
+2dBm
1V/DIV
–10dBm
–20dBm
–30dBm
0
1.230
1.235 1.240
1.245 1.250
VREF (V)
1.255 1.260
1.265 1.270
0
2
4
6
8
10
TIME (ms)
12
14
16
18
20
Figure 37. VREF Distribution
Figure 34. Output Response to Gating on Power Supply for Various RF Input
Levels, Carrier Frequency 900 MHz, CLPF = 0
Rev. B | Page 13 of 36
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