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AD8346ARUZ-REEL71 参数 Datasheet PDF下载

AD8346ARUZ-REEL71图片预览
型号: AD8346ARUZ-REEL71
PDF下载: 下载PDF文件 查看货源
内容描述: 0.8 GHz至2.5 GHz的正交调制器 [0.8 GHz to 2.5 GHz Quadrature Modulator]
分类和应用:
文件页数/大小: 20 页 / 404 K
品牌: ADI [ ADI ]
 浏览型号AD8346ARUZ-REEL71的Datasheet PDF文件第7页浏览型号AD8346ARUZ-REEL71的Datasheet PDF文件第8页浏览型号AD8346ARUZ-REEL71的Datasheet PDF文件第9页浏览型号AD8346ARUZ-REEL71的Datasheet PDF文件第10页浏览型号AD8346ARUZ-REEL71的Datasheet PDF文件第12页浏览型号AD8346ARUZ-REEL71的Datasheet PDF文件第13页浏览型号AD8346ARUZ-REEL71的Datasheet PDF文件第14页浏览型号AD8346ARUZ-REEL71的Datasheet PDF文件第15页  
AD8346  
BASIC CONNECTIONS  
The basic connections for operating the AD8346 are shown in  
Figure 27. A single power supply of between 2.7 V and 5.5 V is  
applied to pins VPS1 and VPS2. A pair of ESD protection  
diodes are connected internally between VPS1 and VPS2 so  
these must be tied to the same potential. Both pins should be  
individually decoupled using 100 pF and 0.01 μF capacitors,  
located as close as possible to the device. For normal operation,  
the enable pin, ENBL, must be pulled high. The turn-on  
threshold for ENBL is 2 V. To put the device in its power-down  
mode, ENBL must be pulled below 0.5 V. Pins COM1 to COM4  
should all be tied to a low impedance ground plane.  
have a bias level about 800 mV below supply. An LO drive  
level of between −6 dBm and −12 dBm is required. For optimal  
performance, a drive level of −10 dBm is recommended,  
although a level of −6 dBm results in more stable temperature  
performance (see Figure 8). Higher levels degrade linearity  
while lower levels tend to increase the noise floor.  
100pF  
LO  
LOIP  
AD8346  
LOIN  
100pF  
The I and Q ports should be driven differentially. This is con-  
venient as most modern high speed DACs have differential  
outputs. For optimal performance, the drive signal should be a  
2 V p-p (differential) signal with a bias level of 1.2 V, that is,  
each input swings from 0.7 V to 1.7 V. The I and Q inputs have  
input impedances of 12 kΩ. By dc coupling the DAC to the  
AD8346 and applying small offset voltages, the LO feedthrough  
can be reduced to well below its nominal value of −42 dBm  
(see Figure 12).  
Figure 26. Single-Ended LO Drive  
The LO terminal can be driven single-ended, as shown in  
Figure 26 at the expense of slightly higher LO feedthrough.  
LOIN is ac coupled to ground using a capacitor and LOIP is  
driven through a coupling capacitor from a (single-ended)  
50 Ω source (this scheme could also be reversed with LOIP  
being ac-coupled to ground).  
LO DRIVE  
RF OUTPUT  
The return loss of the LO port is shown in Figure 18. No add-  
itional matching circuitry is required to drive this port from a  
50 Ω source. For maximum LO suppression at the output, a  
differential LO drive is recommended. In Figure 27, this is  
achieved using a balun (M/A-COM Part Number ETC1-1-13).  
The output of the balun is ac-coupled to the LO inputs which  
The RF output is designed to drive a 50 Ω load, but must be ac-  
coupled, as shown in Figure 27. If the I and Q inputs are driven  
in quadrature by 2 V p-p signals, the resulting output power is  
about −10 dBm (see Figure 7 for variations in output power  
over frequency).  
1
2
3
4
16  
15  
14  
13  
IBBP  
IBBN  
COM1  
COM1  
LOIN  
LOIP  
VPS1  
ENBL  
QP  
QN  
IP  
IN  
QBBP  
QBBN  
AD8346  
COM4  
COM4  
VPS2  
VOUT  
COM3  
COM2  
C6  
100pF  
+V  
S
C1  
100pF  
C2  
0.01μF  
5
4
1
2
3
LO  
5
6
7
8
12  
11  
10  
9
T1  
C7  
100pF  
ETC1-1-13  
VOUT  
C5  
100pF  
+V  
S
C3  
100pF  
C4  
0.01μF  
Figure 27. Basic Connections  
Rev. A | Page 11 of 20