AD8320
LOGIC INPUTS (TTL/CMOS Logic) (DATEN, CLK, SDATA, 5 V ≤ V ≤ 12 V; Full Temperature Range)
CC
P aram eter
Min
Typ
Max
Units
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current (VINH = 5 V) CLK, SDAT A, DATEN
Logic “0” Current (VINL = 0 V) CLK, SDAT A, DATEN
Logic “1” Current (VINH = 5 V) PD
Logic “0” Current (VINL = 0 V) PD
2.1
0
0
–450
0
–320
5.0
0.8
20
–75
190
–70
V
V
nA
nA
µA
µA
(Full Temperature Range, V Supply Range, T = T = 4 ns, FCLK = 8 MHz unless otherwise noted.)
TIMING REQUIREMENTS
P aram eter
CC
R
F
Min
Typ
Max
Units
Clock Pulse Width (TWH
Clock Period (TC)
Setup T ime SDAT A vs. Clock (TDS
Setup T ime DATEN vs. Clock (TES
Hold T ime SDAT A vs. Clock (TDH
)
12.0
32.0
6.5
17.0
5.0
ns
ns
ns
ns
ns
ns
ns
)
)
)
)
Hold T ime DATEN vs. Clock (TEH
Input Rise and Fall T imes, SDAT A, DATEN, Clock (TR, T F)
3.0
10
T
DS
VALID DATA WORD G1
VALID DATA WORD G2
SDATA
CLK
MSB. . . .LSB
T
C
T
WH
EH
T
T
ES
8 CLOCK CYCLES
DATEN
PD
GAIN TRANSFER (G1)
GAIN TRANSFER (G2)
T
OFF
T
GS
T
ON
ANALOG
OUTPUT
PEDESTAL
SIGNAL AMPLITUDE (p-p)
Figure 2. Serial Interface Tim ing
VALID DATA BIT
MSB-1
MSB
MSB-2
T
T
DH
DS
CLK
Figure 3.
–3–
REV. 0
ADI [ ADI ]
