AD8313
APPLICATIONS
BASIC CONNECTIONS FOR LOG (RSSI) MODE
OPERATING IN CONTROLLER MODE
Figure 29 shows the AD8313 connected in its basic measurement
mode. A power supply between 2.7 V and 5.5 V is required. The
power supply to each of the VPOS pins should be decoupled
with a 0.1 µF surface-mount ceramic capacitor and a 10 Ω series
resistor.
Figure 30 shows the basic connections for operation in controller
mode. The link between VOUT and VSET is broken and a set-
point is applied to VSET. Any difference between VSET and the
equivalent input power to the AD8313 drives VOUT either to the
supply rail or close to ground. If VSET is greater than the equivalent
input power, VOUT is driven toward ground, and vice versa.
The PWDN pin is shown as grounded. The AD8313 may be
disabled by a logic high at this pin. When disabled, the chip
current is reduced to about 20 µA from its normal value of
13.7 mA. The logic threshold is at VPOS/2, and the enable
function occurs in about 1.8 µs. However, that additional
settling time is generally needed at low input levels. While the
input in this case is terminated with a simple 50 Ω broadband
resistive match, there are many ways in which the input termi-
nation can be accomplished. These are discussed in the Input
Coupling section.
R1
10Ω
R
PROT
1
2
3
4
8
7
6
5
VPOS VOUT
+V
S
0.1µF
AD8313
INHI
VSET
INLO COMM
PWDN
R3
10Ω
+V
VPOS
S
0.1µF
Figure 30. Basic Connections for Operation in the Controller Mode
This mode of operation is useful in applications where the output
power of an RF power amplifier (PA) is to be controlled by an
analog AGC loop (Figure 31). In this mode, a setpoint voltage,
proportional in dB to the desired output power, is applied to the
VSET pin. A sample of the output power from the PA, via a
directional coupler or other means, is fed to the input of the
AD8313.
VSET is connected to VOUT to establish a feedback path that
controls the overall scaling of the logarithmic amplifier. The
load resistance, RL, should not be lower than 5 kΩ so that the
full-scale output of 1.75 V can be generated with the limited
available current of 400 µA max.
As stated in the Absolute Maximum Ratings table, an externally
applied overvoltage on the VOUT pin, which is outside the
range 0 V to VPOS, is sufficient to cause permanent damage to
the device. If overvoltages are expected on the VOUT pin, a
series resistor, RPROT, should be included as shown. A 500 Ω
resistor is sufficient to protect against overvoltage up to 5 V;
1000 Ω should be used if an overvoltage of up to 15 V is
expected. Since the output stage is meant to drive loads of no
more than 400 μA, this resistor does not impact device perform-
ance for higher impedance drive applications (higher output
current applications are discussed in the Increasing Output
Current section).
ENVELOPE OF
TRANSMITTED
SIGNAL
POWER
AMPLIFIER
RF IN
DIRECTIONAL
COUPLER
AD8313
VOUT
RFIN
SETPOINT
VSET
CONTROL DAC
R1
10Ω
R
PROT
1
2
3
4
8
7
6
5
VPOS VOUT
+V
S
0.1µF
R
= 1MΩ
AD8313
680pF
680pF
L
Figure 31. Setpoint Controller Operation
INHI
VSET
INLO COMM
PWDN
53.6Ω
VOUT is applied to the gain control terminal of the power
amplifier. The gain control transfer function of the power
amplifier should be an inverse relationship, that is, increasing
voltage decreases gain.
R2
10Ω
+V
VPOS
S
0.1µF
Figure 29. Basic Connections for Log (RSSI) Mode
A positive input step on VSET (indicating a demand for increased
power from the PA) drives VOUT toward ground. This should be
arranged to increase the gain of the PA. The loop settles when
VOUT settles to a voltage that sets the input power to the AD8313
to the dB equivalent of VSET
.
Rev. D | Page 15 of 24
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