AD830
Choice of Polarity
The sign of the gain is easily selected by choosing the polarity of
the connections to the + and – inputs of the X G
M
stage. Swap-
ping between inverting and noninverting gain is possible simply
by reversing the input connections. The response of the ampli-
fier is identical in either connection, except for the sign change.
The bandwidth, high impedance, transient behavior, etc., of the
AD830, is symmetrical for both polarities of gain. This is very
advantageous and unlike an op amp.
Input Impedance
the peak output differential voltage can be easily derived from
the maximum output swing as V
OCM
= V
MAX
–V
PEAK
.
Output Current
The relatively high input impedance of the AD830, for a differ-
ential receiver amplifier, permits connections to modest imped-
ance sources without much loading or loss of common-mode
rejection. The nominal input resistance is 300 kΩ. The real limit
to the upper value of the source resistance is in its effect on
common-mode rejection and bandwidth. If the source resistance
is in only one input, then the low frequency common-mode re-
jection will be lowered to
≈
R
IN
/R
S
. The source resistance/input
1
capacitance pole
f
=
2π
×
R
S
×
C
IN
limits the bandwidth.
Furthermore, the high frequency common-mode rejection will
be additionally lowered by the difference in the frequency re-
sponse caused by the R
S
C
IN
pole. Therefore, to maintain
good low and high frequency common-mode rejection, it is rec-
ommended that the source resistances of the + and – inputs be
matched and of modest value (≤10 kΩ).
The absolute peak output current is set by the short circuit cur-
rent limiting, typically greater that 60 mA. The maximum drive
capability is rated at 50 mA, but without a guarantee of distor-
tion performance. Best distortion performance is obtained by
keeping the output current
≤20
mA. Attempting to drive large
voltages into low valued resistances (e.g., 10 V into 150
Ω)
will
cause an apparent lowering of the limit for output signal swing,
but is just the current limiting behavior.
Driving Cap Loads
The AD830 is capable of driving modest sized capacitive loads
while maintaining its rated performance. Several curves of band-
width versus capacitive load are given in Figures 15 and 18. The
AD830 was designed primarily as a low distortion video speed
amplifier, but with a tradeoff, giving up very large capacitive
load driving capability. If very large capacitive loads must be
driven, then the network shown in Figure 27 should be used to
insure stable operation. If the loss of gain caused by the resistor
R
S
in series with the load is objectionable, then the optional
feedback network shown may be added to restore the lost gain.
+V
S
1
V
CM
+
INPUT
SIGNAL
–
G
M
AD830
8
0.1µF
R
S
36.5Ω
V
OUT
The bias currents are typically 4
µA
flowing into each pin of the
G
M
stages of the AD830. Since all applications possess some fi-
nite source resistance, the bias current through this resistor will
create a voltage drop (I
BIAS
R
S
). The relatively high input im-
pedance of the AD830 permits modest values of R
S
, typically
≤10
kΩ. If the source resistance is in only one terminal, then an
objectional offset voltage may result (e.g., 4
µA
5 kΩ =
20 mV). Placement of an equal value resistor in series with the
other input will cancel the offset to first order. However, due to
mismatches in the resistances, a residual offset will remain and
likely be greater than bias current (offset current) mismatches.
Applying Feedback
Handling Bias Currents
2
Z
CM
A=1
7
C
1
100pF
R
1
1kΩ
3
C
G
M
6
* OPTIONAL
FEEDBACK
NETWORK
0.1µF
–V
S
R
S
4
5
CLOSED-LOOP AMPLITUDE RESPONSE – dB
The AD830 is intended for use with gain from 1 to 100. Gains
greater than one are simply set by a pair of resistors connected
as shown in the difference amplifier (Figure 35) with gain >1.
The value of the bottom resistor R
2
, should be kept less than
1 kΩ to insure that the pole formed by C
IN
and the parallel con-
nection of R
1
and R
2
is sufficiently high in frequency so that it
does not introduce excessive phase shift around the loop and de-
stabilizes the amplifier. A compensating resistor, equal to the
parallel combination of R
1
and R
2
, should be placed in series
with the other Y G
M
stage input to preserve the high frequency
common-mode rejection and to lower the offset voltage induced
by the input bias current.
Output Common Mode
R
1
Figure 27. Circuit for Driving Large Capacitive Loads
3
0
–3
–6
–9
–12
–15
–18
–21
–24
–27
10k
±5V
±15V
The output swing of the AD830 is defined by the differential in-
put voltage, the gain and the output common. Depending on
the anticipated signal span, the output common (or ground)
may be set anywhere between the allowable peak output voltage
in a manner similar to that described for input voltage common
mode. A plot of the peak output voltage versus supply is shown
in Figure 26. A prediction of the common-mode range versus
100k
1M
FREQUENCY – Hz
10M
100M
Figure 28. Closed-Loop Response vs. Frequency with
100 pF Load and Series Resistor Compensation
REV. A
–11–
AD [ ANALOG DEVICES ]
