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AD820AR 参数 Datasheet PDF下载

AD820AR图片预览
型号: AD820AR
PDF下载: 下载PDF文件 查看货源
内容描述: 单电源,轨至轨低功耗FET输入运算放大器 [Single Supply, Rail to Rail Low Power FET-Input Op Amp]
分类和应用: 运算放大器
文件页数/大小: 16 页 / 240 K
品牌: AD [ ANALOG DEVICES ]
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AD820
APPLICATION NOTES
INPUT CHARACTERISTICS
In the AD820, n-channel JFETs are used to provide a low off-
set, low noise, high impedance input stage. Minimum input
common-mode voltage extends from 0.2 V below –V
S
to 1 V
less than +V
S
. Driving the input voltage closer to the positive
rail will cause a loss of amplifier bandwidth (as can be seen by
comparing the large signal responses shown in Figures 28 and
31) and increased common-mode voltage error as illustrated in
Figure 19.
The AD820 does not exhibit phase reversal for input voltages
up to and including +V
S
. Figure 38a shows the response of an
AD820 voltage follower to a 0 V to +5 V (+V
S
) square wave
input. The input and output are superimposed. The output
polarity tracks the input polarity up to +V
S
—no phase reversal.
The reduced bandwidth above a 4 V input causes the rounding
of the output wave form. For input voltages greater than +V
S
, a
resistor in series with the AD820’s plus input will prevent phase
reversal, at the expense of greater input voltage noise. This is
illustrated in Figure 38b.
Since the input stage uses n-channel JFETs, input current dur-
ing normal operation is negative; the current flows out from the
input terminals. If the input voltage is driven more positive than
+V
S
– 0.4 V, the input current will reverse direction as internal
device junctions become forward biased. This is illustrated in
Figure 6.
A current limiting resistor should be used in series with the
input of the AD820 if there is a possibility of the input voltage
exceeding the positive supply by more than 300 mV, or if an
input voltage will be applied to the AD820 when
±
V
S
= 0. The
amplifier will be damaged if left in that condition for more than
10 seconds. A 1 kΩ resistor allows the amplifier to withstand up
to 10 volts of continuous overvoltage, and increases the input
voltage noise by a negligible amount.
Input voltages less than –V
S
are a completely different story.
The amplifier can safely withstand input voltages 20 volts below
the minus supply voltage as long as the total voltage from the
positive supply to the input terminal is less than 36 volts. In
addition, the input stage typically maintains picoamp level input
currents across that input voltage range.
The AD820 is designed for 13 nV/√Hz wideband input voltage
noise and maintains low noise performance to low frequencies
(refer to Figure 13). This noise performance, along with the
AD820’s low input current and current noise means that the
AD820 contributes negligible noise for applications with source
resistances greater than 10 kΩ and signal bandwidths greater
than 1 kHz. This is illustrated in Figure 39.
100k
WHENEVER JOHNSON NOISE IS GREATER THAN
AMPLIFIER NOISE, AMPLIFIER NOISE CAN BE
CONSIDERED NEGLIGIBLE FOR APPLICATION.
1kHz
1k
RESISTOR JOHNSON
NOISE
100
INPUT VOLTAGE NOISE –
V
RMS
10k
10
10Hz
1
AMPLIFIER-GENERATED
NOISE
GND
0.1
10k
100k
1M
10M
100M
SOURCE IMPEDANCE –
1G
10G
(a)
Figure 39. Total Noise vs. Source Impedance
OUTPUT CHARACTERISTICS
+V
S
GND
(b)
+5V
R
P
V
IN
The AD820’s unique bipolar rail-to-rail output stage swings
within 5 mV of the minus supply and 10 mV of the positive
supply with no external resistive load. The AD820’s approxi-
mate output saturation resistance is 40
sourcing and 20
sinking. This can be used to estimate output saturation voltage
when driving heavier current loads. For instance, when sourcing
5 mA, the saturation voltage to the positive supply rail will be
200 mV, when sinking 5 mA, the saturation voltage to the
minus rail will he 100 mV.
The amplifier’s open-loop gain characteristic will change as a
function of resistive load, as shown in Figures 9 through 12. For
load resistances over 20 kΩ, the AD820’s input error voltage is
virtually unchanged until the output voltage is driven to 180 mV
of either supply.
If the AD820’s output is driven hard against the output satura-
tion voltage, it will recover within 2
µs
of the input returning to
the amplifier’s linear operating region.
AD820
V
OUT
Figure 38. (a) Response with R
P
= 0; V
IN
from 0 to +V
S
Figure 36.
(b) V
IN
= 0 to +V
S
+ 200 mV
V
OUT
= 0 to +V
S
R
P
= 49.9 k
REV. B
–13–