AD817
O FFSET NULLING
Measuring the rapid settling time of AD817 (45 ns to 0.1% and
70 ns to 0.01%–10 V step) requires applying an input pulse with
a very fast edge and an extremely flat top. With the AD817 con-
figured in a gain of –1, a clamped false summing junction re-
sponds when the output error is within the sum of two diode
voltages (ª1 volt). T he signal is then amplified 20 times by a
clamped amplifier whose output is connected directly to a sam-
pling oscilloscope. Figures 33 and 34 show the settling time of
the AD817, with a 10 volt step applied.
T he input offset voltage of the AD817 is inherently very low.
However, if additional nulling is required, the circuit shown in
Figure 32 can be used. T he null range of the AD817 in this con-
figuration is ±15 mV.
AD 817 SETTLING TIME
Settling time is comprised primarily of two regions. T he first is
the slew time in which the amplifier is overdriven, where the
output voltage rate of change is at its maximum. T he second is
the linear time period required for the amplifier to settle to
within a specified percent of the final value.
0
–2
–4
–6
–8
–10
10
8
6
4
0.20
0.15
0.10
0.05
0
2
0
0.05
0
0.05
0.05
0.10
0.15
0.20
0
50
100 150 200 250 300 350 400
Figure 34. Settling Tim e in ns 0 V to –10 V
0
50
100 150 200 250 300 350 400
Figure 33. Settling Tim e in ns 0 V to +10 V
2×
HP2835
15pF
1MΩ
ERROR AMPLIFIER
V
OUTPUT × 10
ERROR
5
3
2
100Ω
2×
HP2835
SETTLING
OUTPUT
AD829
6
0.47µF
4
SHORT, DIRECT
7
CONNECTION TO
0.01µF
0.47µF
TEKTRONIX TYPE 11402
OSCILLOSCOPE PREAMP
INPUT SECTION
0.01µF
ERROR
SIGNAL
OUTPUT
+V
–V
S
S
100Ω
1.9kΩ
0 TO ±10V
POWER
SUPPLY
NOTE:
USE CIRCUIT BOARD
WITH GROUND PLANE
EI&S
DL1A05GM
MERCURY RELAY
FALSE
SUMMING
NODE
NULL
ADJUST
7, 8
1kΩ
100Ω
1kΩ
500Ω
2
50Ω
COAX
CABLE
DEVICE
UNDER
TEST
13
TTL LEVEL
5–18pF
SIGNAL
GENERATOR
50Hz
TEKTRONIX P6201
FET PROBE TO
TEKTRONIX TYPE
11402
1, 14
500Ω
2
3
OUTPUT
6
AD817
50Ω
OSCILLOSCOPE
PREAMP INPUT
SECTION
10pF
SCOPE PROBE
CAPACITANCE
7
4
0.01µF
2.2µF
DIGITAL
GROUND
0.01µF
2.2µF
+V
S
ANALOG
GROUND
–V
S
Figure 35. Settling Tim e Test Circuit
–10–
REV. B
ADI [ ADI ]
