AD8139
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage
V
OCM
Power Dissipation
Input Common-Mode Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering 10 sec)
Junction Temperature
Rating
12 V
±V
S
See Figure 4
±V
S
−65°C to +125°C
−40°C to +125°C
300°C
150°C
The power dissipated in the package (P
D
) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (V
S
) times the
quiescent current (I
S
). The load current consists of differential
and common-mode currents flowing to the load, as well as
currents flowing through the external feedback networks and
the internal common-mode feedback loop. The internal resistor
tap used in the common-mode feedback loop places a 1 kΩ
differential load on the output. RMS output voltages should be
considered when dealing with ac signals.
Airflow reduces θ
JA
. In addition, more metal directly in contact
with the package leads from metal traces, through holes,
ground, and power planes reduce the θ
JA
.
package vs. the ambient temperature for the exposed paddle
(EP) 8-lead SOIC (θ
JA
= 70°C/W) and the 8-lead LFCSP
(θ
JA
= 70°C/W) on a JEDEC standard 4-layer board. θ
JA
values
are approximations.
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
04679-055
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, that is, θ
JA
is
specified for device soldered in circuit board for surface-mount
packages.
Table 4.
Package Type
8-Lead SOIC with EP/4-Layer
8-Lead LFCSP/4-Layer
θ
JA
70
70
Unit
°C/W
°C/W
MAXIMUM POWER DISSIPATION (W)
Maximum Power Dissipation
The maximum safe power dissipation in the AD8139 package
is limited by the associated rise in junction temperature (T
J
) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic will change its properties. Even
temporarily exceeding this temperature limit can change the
stresses that the package exerts on the die, permanently shifting
the parametric performance of the AD8139. Exceeding a junction
temperature of 175°C for an extended period can result in
changes in the silicon devices potentially causing failure.
SOIC
AND LFCSP
0
–40
–20
0
20
40
60
80
100
120
AMBIENT TEMPERATURE (°C)
Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
Rev. B | Page 7 of 24
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