AD8138
V
S
=
5V
V
OUT,dm
= 2V p-p
C
F
= 0pF
C
F
= 0pF
V
OUT,dm
= 2V p-p
V
S
= 5V
200 V
V
S
= 5V
C
F
= 1pF
V
OUT,dm
V
S
= +5V
C
F
= 1pF
V
+DIN
400mV
5ns
400mV
5ns
1V
4ns
Figure 20. Large Signal Transient
Response
Figure 21. Large Signal Transient
Response
Figure 22. Settling Time
V
S
= 5V
C
F
= 0pF
V
OUT,dm
C
L
= 5pF
C
L
= 10pF
499
V
S
= 5V
F = 20MHz
V
+DIN
= 8V p-p
G = 3(R
F
= 1500)
499
49.9
499
24.9
24.9
C
L
= 20pF
AD8138
499
24.9
C
L
453
V
+DIN
4V
30ns
400mV
2.5ns
Figure 23. Output Overdrive
Figure 24. Test Circuit for Cap Load
Drive
Figure 25. Large Signal Transient
Response for Various Cap Loads
–20
–20
–30
V
S
= 5V
V
OUT,dm
/ V
IN
,
cm
V
IN
= 2V p-p
–30
–40
CMRR – dB
499
499
49.9
499
24.9
249
BALANCE ERROR – dB
–40
V
S
=
–50
5V
–50
–60
AD8138
499
249
–70
–80
1
10
100
FREQUENCY – MHz
1k
–60
V
S
= +5V
–70
1
10
100
FREQUENCY – MHz
1k
Figure 26. CMRR vs. Frequency
Figure 27. Test Circuit for Output
Balance
Figure 28. Output Balance Error vs.
Frequency
REV. A
–7–
AD [ ANALOG DEVICES ]
