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AD8138AR 参数 Datasheet PDF下载

AD8138AR图片预览
型号: AD8138AR
PDF下载: 下载PDF文件 查看货源
内容描述: 低失真差分ADC驱动器 [Low Distortion Differential ADC Driver]
分类和应用: 线路驱动器或接收器驱动程序和接口接口集成电路光电二极管
文件页数/大小: 14 页 / 235 K
品牌: ADI [ ADI ]
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AD8138  
HIGH PERFORMANCE ADC DRIVING  
The signal generator has a ground-referenced, bipolar output,  
i.e., it drives symmetrically above and below ground. Connect-  
ing VOCM to the CML pin of the AD9224 sets the output com-  
mon- mode of the AD8138 at 2.5 V, which is the midsupply  
level for the AD9224. This voltage is bypassed by a 0.1 µF  
capacitor.  
The circuit in Figure 40 shows a simplified front-end connec-  
tion for an AD8138 driving an AD9224, a 12-bit, 40 MSPS  
A/D converter. The A/D works best when driven differentially,  
which minimizes its distortion as described in its data sheet.  
The AD8138 eliminates the need for a transformer to drive the  
ADC and performs single-ended-to-differential conversion,  
common-mode level-shifting and buffering of the driving signal.  
The full-scale analog input range of the AD9224 is set to 4 V p-p,  
by shorting the SENSE terminal to AVSS. This has been deter-  
mined to be the scaling to provide minimum harmonic distortion.  
The positive and negative outputs of the AD8138 are connected  
to the respective differential inputs of the AD9224 via a pair of  
49.9 resistors to minimize the effects of the switched-capaci-  
tor front-end of the AD9224. For best distortion performance it  
is run from supplies of ±5 V.  
For the AD8138 to swing a 4 V p-p, each output swings 2 V p-p,  
while providing signals that are 180 degrees out of phase. With a  
common-mode voltage at the output of 2.5 V, this means that  
each AD8138 output will swing between 1.5 V and 3.5 V  
The AD8138 is configured with unity gain for a single-ended  
input-to-differential output. The additional 23 , 523 total,  
at the input to –IN is to balance the parallel impedance of the  
50 source and its 50 termination that drives the noninverting  
input.  
A ground-referenced 4 V p-p, 5 MHz signal at DIN+ was used  
to test the circuit in Figure 40. When the combined-device  
circuit was run with a sampling rate of 20 MHz MSPS, the  
SFDR (spurious free dynamic range) was measured at –85 dBc.  
+5V  
+5V  
0.1pF  
0.1pF  
499  
49.9⍀  
49.9⍀  
499⍀  
AVDD DRVDD  
+
VINB  
DIGITAL  
OUTPUTS  
V
OCM  
AD9224  
500⍀  
SOURCE  
49.9⍀  
AD8138  
523⍀  
VINA  
AVSS SENSE CML DRVSS  
0.1pF  
499⍀  
–5V  
Figure 40. AD8138 Driving an AD9224, a 12-Bit, 40 MSPS A/D Converter  
–12–  
REV. A