AD8138
When using the AD8138 in gain configurations where
In the case of a single-ended input signal (for example if –DIN is
grounded and the input signal is applied to +DIN), the input
impedance becomes:
RF
RG
Ê
ˆ
of one feedback network is unequal to
Á
˜
RG
RF
RIN,dm
=
Á
˜
RF
RG
Á
Á
Ë
˜
˜
¯
1-
2 ¥ R + RF
(
)
G
of the other network, there will be a differential output noise
due to input-referred voltage in the VOCM circuitry. The output
noise is defined in terms of the following feedback terms (refer
to Figure 2):
The circuit’s input impedance is effectively higher than it would
be for a conventional op amp connected as an inverter because a
fraction of the differential output voltage appears at the inputs
as a common-mode signal, partially bootstrapping the voltage
across the input resistor RG.
RG
b1 =
RF + RG
Input Common-Mode Voltage Range in Single-Supply
Applications
for –OUT to +IN loop, and
The AD8138 is optimized for level-shifting “ground” referenced
input signals. For a single-ended input, this would imply, for
example, that the voltage at –DIN in Figure 2 would be 0 V when
the amplifier’s negative power supply voltage (at V–) is also
set to 0 V.
RG
b2 =
RF + RG
for +OUT to –IN loop. With these defined,
Setting the Output Common-Mode Voltage
È
˘
b1 – b2
b1 + b2
VnOUT ,dm = 2V
nIN ,VOCM
The AD8138’s VOCM pin is internally biased at a voltage approxi-
mately equal to the midsupply point (average value of the voltages
on V+ and V–). Relying on this internal bias will result in an
output common-mode voltage that is within about 100 mV of
the expected value.
Í
Î
˙
˚
where VnOUT,dm is the output differential noise and VnIN,V
the input-referred voltage noise in VOCM
is
OCM
.
The Impact of Mismatches in the Feedback Networks
In cases where more accurate control of the output common-mode
level is required, it is recommended that an external source, or
resistor divider (made up of 10 kW resistors), be used. The output
common-mode offset listed in the Specifications section assumes
the VOCM input is driven by a low impedance voltage source.
As mentioned previously, even if the external feedback networks
(RF/RG) are mismatched, the internal common-mode feedback
loop will still force the outputs to remain balanced. The ampli-
tudes of the signals at each output will remain equal and 180Њ
out of phase. The input-to-output differential-mode gain will
vary proportionately to the feedback mismatch, but the output
balance will be unaffected.
Driving a Capacitive Load
A purely capacitive load can react with the pin and bondwire
inductance of the AD8138, resulting in high frequency ringing
in the pulse response. One way to minimize this effect is to place
a small capacitor across each of the feedback resistors. The added
capacitance should be small to avoid destabilizing the amplifier.
An alternative technique is to place a small resistor in series with
the amplifier’s outputs as shown in TPC 23.
Ratio matching errors in the external resistors will result in a
degradation of the circuit’s ability to reject input common-mode
signals, much the same as for a four-resistor difference amplifier
made from a conventional op amp.
Also, if the dc levels of the input and output common-mode
voltages are different, matching errors will result in a small
differential-mode output offset voltage. For the G = 1 case, with
a ground referenced input signal and the output common-mode
level set for 2.5 V, an output offset of as much as 25 mV (1% of
the difference in common-mode levels) can result if 1% tolerance
resistors are used. Resistors of 1% tolerance will result in a worst-
case input CMRR of about 40 dB, worst-case differential mode
output offset of 25 mV due to 2.5 V level-shift, and no significant
degradation in output balance error.
LAYOUT, GROUNDING, AND BYPASSING
As a high speed part, the AD8138 is sensitive to the PCB
environment in which it has to operate. Realizing its superior
specifications requires attention to various details of good high
speed PCB design.
The first requirement is for a good solid ground plane that covers
as much of the board area around the AD8138 as possible. The
only exception to this is that the two input pins (Pins 1 and 8)
should be kept a few millimeters from the ground plane, and
ground should be removed from inner layers and the opposite
side of the board under the input pins. This will minimize the
stray capacitance on these nodes and help preserve the gain
flatness versus frequency.
Calculating an Application Circuit’s Input Impedance
The effective input impedance of a circuit such as the one in
Figure 2, at +DIN and –DIN, will depend on whether the amplifier
is being driven by a single-ended or differential signal source.
For balanced differential input signals, the input impedance
(RIN,dm) between the inputs (+DIN and –DIN) is simply:
RIN,dm = 2 ¥ RG
–10–
REV. E
ADI [ ADI ]
