AD8055/AD8056
Power Dissipation Limits
5
4
402⍀
With a 10 V supply (total VCC – VEE), the quiescent power dissi-
pation of the AD8055 in the SOT-23-5 package is 65 mW,
while the quiescent power dissipation of the AD8056 in the
microSOIC is 120 mW. This translates into a 15.6°C rise above
the ambient for the SOT-23-5 package and a 24°C rise for the
microSOIC package.
402⍀
C
= 30pF
L
3
CL
100⍀
VIN = 0dBm
2
50⍀
1
0
The power dissipated under heavy load conditions is approxi-
mately equal to the supply voltage minus the output voltage,
times the load current, plus the quiescent power computed above.
This total power dissipation is then multiplied by the thermal
resistance of the package to find the temperature rise, above
ambient, of the part. The junction temperature should be kept
below 150°C.
C
= 20pF
= 10pF
L
–1
–2
–3
–4
–5
C
L
C
= 0pF
L
0.3
1
10
FREQUENCY – MHz
100
500
The AD8055 in the SOT-23-5 package can dissipate 270 mW
while the AD8056 in the microSOIC package can dissipate
325 mW (at 85°C ambient) without exceeding the maximum
die temperature. In the case of the AD8056, this is greater than
1.5 V rms into 50 Ω, enough to accommodate a 4 V p-p sine-wave
signal on both outputs simultaneously. But since each output of
the AD8055 or AD8056 is capable of supplying as much as
110 mA into a short circuit, a continuous short circuit condition
will exceed the maximum safe junction temperature.
Figure 36. Capacitive Load Drive
In general, to minimize peaking or to ensure the stability for
larger values of capacitive loads, a small series resistor, RS, can
be added between the op amp output and the capacitor, CL. For
the setup depicted in Figure 37, the relationship between RS and
CL was empirically derived and is shown in Figure 38. RS was
chosen to produce less than 1 dB of peaking in the frequency
response. Note also that after a sharp rise RS quickly settles to
about 25 Ω.
Resistor Selection
The following table is provided as a guide to resistor selection
for maintaining gain flatness vs. frequency for various values of
gain.
402⍀
+5V
0.1F
10F
–3 dB
Bandwidth
(MHz)
402⍀
7
2
3
FET PROBE
R
S
V
6
AD8055
Gain
RF (⍀)
RI (⍀)
OUT
C
L
4
V
= 0dBm
IN
+1
+2
+5
+10
0
402
1k
—
300
160
45
50⍀
10F
402
249
100
0.1F
–5V
909
20
Figure 37. Setup for RS vs. CL
Driving Capacitive Loads
40
35
30
25
20
15
10
5
When driving a capacitive load, most op amps will exhibit peak-
ing in the frequency response just before the frequency rolls off.
Figure 36 shows the responses for an AD8056 running at a gain
of +2, with a 100 Ω load that is shunted by various values of
capacitance. It can be seen that under these conditions, the part
is still stable with capacitive loads of up to 30 pF.
0
0
10
20
30
40
– pF
50
60
270
C
L
Figure 38. RS vs. CL
REV. B
–10–
ADI [ ADI ]
