AD8051/AD8052/AD8054
ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG
APPLICATIONS
used as a driver
for an
a 10-bit, 20 MSPS, dual analog-to-digital
converter. This converter is designed to convert I and Q signals in
communications systems. In this application, only the I channel
is being driven. The I channel is enabled by applying a logic
high to SELECT (Pin 13).
The AD8051 is running from a dual supply and is configured
for a gain of +2. The input signal is terminated in 50 Ω and the
output is 2 V p-p, which is the maximum input range of the
that flows and helps to lower the distortion of the ADC.
The AD9201 has differential inputs for each channel. These are
designated the A and B inputs. The B inputs of each channel are
connected to VREF (Pin 22), which supplies a positive reference
of 2.5 V. Each of the B inputs has a small low-pass filter that also
helps to reduce distortion.
The output of the op amp is ac-coupled into INA-I (Pin 16) via
two parallel capacitors to provide good high frequency and low
frequency coupling. The 1 kΩ resistor references the signal to
VREF that is applied to INB-I. Thus, INA-I swings both positive
and negative with respect to the bias voltage applied to INB-I.
With the sampling clock running at 20 MSPS, the analog-to-
digital output was analyzed with a digital analyzer. Two input
frequencies were used, 1 MHz and 9.5 MHz, which is just short
of the Nyquist frequency. These signals were well filtered to
minimize any harmonics.
1 MHz analog input. The SFDR is 71.66 dB, and the analog-to-
digital is producing 8.8 ENOB (effective number of bits). When
the analog frequency was raised to 9.5 MHz, the SFDR was
0.33µF
+5V
0.1µF
3
7
reduced to −60.18 dB and the ADC operated with 8.46 ENOBs
as shown in Figure 49. The inclusion of the AD8051 in the
circuit did not worsen the distortion performance of the AD9201.
10
0
–10
–20
AMPLITUDE (dB)
FUND
PART#
0
FFTSIZE 8192
FCLK
20.0MHz
FUND
998.5kHz
VIN
THD
SNR
–0.51dB
–68.13
54.97
–30
–40
–50
–60
–70
–80
–90
2ND
3RD
4TH
5TH
6TH
7TH
8TH
9TH
SINAD
54.76
ENOB
8.80
SFDR
71.66
2ND
3RD
4TH
5TH
6TH
7TH
8TH
9TH
–74.53
–76.06
–76.35
–79.05
–80.36
–75.08
–88.12
01062-049
01062-050
–100
–110
–120
0
1
2
3
4
5
6
7
FREQUENCY (MHz)
8
9
10
–77.87
Figure 48. FFT Plot for AD8051 Driving the AD9201 at 1 MHz
10
0
–10
–20
AMPLITUDE (dB)
FUND
PART#
FCLK
FUND
VIN
THD
SNR
0
20.0MHz
9.5MHz
–0.44dB
–57.08
54.65
FFTSIZE 8192
–30
–40
–50
–60
–70
–80
–90
2ND
3RD
SINAD
52.69
ENOB
8.46
SFDR
2ND
4TH
6TH
8TH
7TH
5TH
60.18
–60.18
–60.23
–82.01
–78.83
–81.28
–77.28
–84.54
–92.78
3RD
4TH
5TH
6TH
7TH
8TH
9TH
–100
–110
–120
0
1
2
3
4
5
6
7
FREQUENCY (MHz)
8
9
10
Figure 49. FFT Plot for AD8051 Driving the AD9201 at 9.5 MHz
22Ω
1kΩ
10pF
22Ω
10pF
0.1µF
10µF
0.1µF
0.1µF
15
16
SLEEP
INA-I
INB-I
REFT-I
REFB-I
AVSS
REFSENSE
VREF
AVDD
REFB-Q
REFT-Q
CLOCK
14
SELECT
13
+V
DD
10µF
0.01µF
22Ω
17
AD9201
D9
12
D8
11
D7
10
D6
9
D5
8
D4
7
DATA OUT
18
19
50Ω
2
AD8051
4
6
1kΩ
20
21
0.1µF
–5V
10µF
+5V
1kΩ
10µF
10µF
0.1µF
0.1µF
0.1µF
0.1µF
22
23
D3
6
D2
5
D1
4
D0
3
10µF
0.1µF
22Ω
24
25
26
INB-Q
INA-Q
CHIP–SELECT
DVDD
2
DVSS
1
0.1µF
10µF
+5V
10pF
22Ω
10pF
27
28
Figure 50. The AD8051 Driving an AD9201, a 10-Bit, 20 MSPS Analog-to-Digital Converter
Rev. H | Page 19 of 24
01062-048
AD [ ANALOG DEVICES ]
