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AD797ARZ-REEL 参数 Datasheet PDF下载

AD797ARZ-REEL图片预览
型号: AD797ARZ-REEL
PDF下载: 下载PDF文件 查看货源
内容描述: 超低失真,超低噪声运算放大器 [Ultralow Distortion, Ultralow Noise Op Amp]
分类和应用: 运算放大器
文件页数/大小: 20 页 / 514 K
品牌: ADI [ ADI ]
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AD797  
20pF TO 120pF  
100  
DRIVING CAPACITIVE LOADS  
R
1
The capacitive load driving capabilities of the AD797 are  
displayed in Figure 41. At gains greater than 10, usually no  
special precautions are necessary. If more drive is desirable,  
however, the circuit shown in Figure 42 should be used. For  
example, this circuit allows a 5000 pF load to be driven cleanly  
at a noise gain ≥2.  
+V  
S
*
I
IN  
2
3
7
6
*
AD797  
600Ω  
4
100nF  
C
R
S
S
–V  
S
10nF  
1nF  
*USE THE POWER SUPPLY BYPASSING SHOWN IN FIGURE 35.  
Figure 39. I-to-V Converter Connection  
THE INVERTING CONFIGURATION  
The inverting configuration (see Figure 40) presents a low input  
impedance, R1, to the source. For this reason, the goals of both  
low noise and input buffering are at odds with one another.  
Nonetheless, the excellent dynamics of the AD797 makes  
it the preferred choice in many inverting applications, and  
with careful selection of feedback resistors, the noise penalties  
are minimal. Some examples are presented in Table 5 and  
Figure 40.  
100pF  
10pF  
1pF  
1
10  
100  
1k  
CLOSED-LOOP GAIN  
Figure 41. Capacitive Load Drive Capability vs. Closed-Loop Gain  
C
L
20pF  
R
2
1k  
+V  
7
S
200pF  
100Ω  
*
R1  
+V  
S
2
3
*
6
*
AD797  
1kΩ  
2
3
7
R
L
4
33Ω  
6
*
AD797  
R
S
C1  
4
–V  
S
*USE THE POWER SUPPLY BYPASSING SHOWN IN FIGURE 35.  
–V  
S
Figure 40. Inverting Amplifier Connection  
*USE THE POWER SUPPLY BYPASSING SHOWN IN FIGURE 35.  
Table 5. Values for Inverting Circuit  
Figure 42. Recommended Circuit for Driving a High Capacitance Load  
Noise  
SETTLING TIME  
Gain  
−ꢀ  
−ꢀ  
R1  
R2  
CL  
(Excluding RS)  
3.0 nV/√Hz  
ꢀ.8 nV/√Hz  
ꢀ.8 nV/√Hz  
The AD797 is unique among ultralow noise amplifiers in that it  
settles to 16 bits (<150 μV) in less than 800 ns. Measuring this  
performance presents a challenge. A special test circuit (see  
Figure 43) was developed for this purpose. The input signal was  
obtained from a resonant reed switch pulse generator, available  
from Tektronix as calibration Fixture No. 067-0608-00. When  
open, the switch is simply 50 Ω to ground and settling is purely  
a passive pulse decay and inherently flat. The low repetition rate  
signal was captured on a digital oscilloscope after being  
ꢀ kΩ  
300 Ω  
ꢀ±0 Ω  
ꢀ kΩ  
300 Ω  
ꢀ±00 Ω  
≈20 pF  
≈ꢀ0 pF  
≈± pF  
−ꢀ0  
amplified and clamped twice. The selection of plug-in for the  
oscilloscope was made for minimum overload recovery.  
Rev. F | Page ꢀ4 of 20  
 
 
 
 
 
 
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