AD797
THEORY OF OPERATION
The architecture of the AD797 was developed to overcome
inherent limitations in previous amplifier designs. Previous
precision amplifiers used three stages to ensure high open-loop
gain (see Figure 30) at the expense of additional frequency com-
pensation components. Slew rate and settling performance are
usually compromised, and dynamic performance is not adequate
beyond audio frequencies. As can be seen in Figure 30, the first
stage gain is rolled off at high frequencies by the compensation
network. Second stage noise and distortion then appears at the
input and degrade performance. The AD797, on the other hand,
uses a single ultrahigh gain stage to achieve dc as well as dynamic
precision. As shown in the simplified schematic (Figure 31),
Node A, Node B, and Node C track the input voltage, forcing
the operating points of all pairs of devices in the signal path to
match. By exploiting the inherent matching of devices fabricated on
the same IC chip, high open-loop gain, CMRR, PSRR, and low
benefit of making the low noise of the AD797 (<0.9 nV/√Hz)
extend to beyond 1 MHz. This means new levels of perform-
ance for sampled data and imaging systems. All of this
performance as well as load drive in excess of 30 mA are made
possible by the Analog Devices, Inc., advanced complementary
bipolar (CB) process.
Another unique feature of this circuit is that the addition of a
single capacitor, CN (see Figure 31), enables cancellation of
distortion due to the output stage. This can best be explained by
referring to a simplified representation of the AD797 using
idealized blocks for the different circuit elements (Figure 32).
A single equation yields the open-loop transfer function of this
amplifier; solving it at Node B yields
VOUT
VIN
gm
=
CN
A
CC
A
jω − CN jω −
jω
VOS are guaranteed by pairwise device matching (that is, NPN
to NPN and PNP to PNP), not by an absolute parameter such as
beta and the early voltage.
where:
gm is the transconductance of Q1 and Q2.
A is the gain of the output stage (~1).
BUFFER
V
OUT
g
V
V
OUT is voltage at the output.
IN is differential input voltage.
m
R
R1
C1
L
When CN is equal to CC, the ideal single-pole op amp response
is attained:
6
GAIN = g × R1 × 5 × 10
m
a.
VOUT
VIN
gm
jωC
C2
=
BUFFER
V
g
A2
C1
A3
OUT
m
In Figure 32, the terms of Node A, which include the properties of
the output stage, such as output impedance and distortion, cancel
by simple subtraction. Therefore, the distortion cancellation does
not affect the stability or frequency response of the amplifier. With
only 500 μA of output stage bias, the AD797 delivers a 1 kHz
sine wave into 60 Ω at 7 V rms with only 1 ppm of distortion.
R1
R
L
R2
GAIN = g × R1 × A2 × A3
m
b.
Figure 30. Model of AD797 vs. That of a Typical Three-Stage Amplifier
V
CC
I1
I2
C
R2
R3
N
C
N
R1
I5
Q4
Q10
Q11
Q3
Q7
A
B
A
B
V
A
OUT
Q9
V
OUT
+IN
–IN
+IN
–IN
Q12 Q8
C
C
CURRENT
MIRROR
Q1 Q2
C
C
Q5
C
Q6
Q1
Q2
1
I6
I1
I7
I4
I3
C
I4
V
SS
Figure 31. AD797 Simplified Schematic
Figure 32. AD797 Block Diagram
This matching benefits not just dc precision, but, because it holds
up dynamically, both distortion and settling time are also reduced.
This single stage has a voltage gain of >5 × 106 and VOS < 80 μV,
while at the same time providing a THD + noise of less than
−120 dB and true 16-bit settling in less than 800 ns. The
elimination of second-stage noise effects has the additional
NOISE AND SOURCE IMPEDANCE
CONSIDERATIONS
The AD797 ultralow voltage noise of 0.9 nV/√Hz is achieved
with special input transistors running at nearly 1 mA of
collector current. Therefore, it is important to consider the total
input-referred noise (eNtotal), which includes contributions
Rev. F | Page ꢀꢀ of 20
ADI [ ADI ]
