AD7943/AD7945/AD7948
AD7945 TIMING SPECIFICATIONS
1
(T = T
A
MIN
to T
MAX
,
unless otherwise noted)
Units
ns min
ns min
ns min
ns min
ns min
Description
Data Setup Time
Data Hold Time
Chip Select Setup Time
Chip Select Hold Time
Write Pulsewidth
Parameter
t
DS
t
DH
t
CS
t
CH
t
WR
Limit @
V
DD
= +3 V to +3.6 V
35
10
60
0
60
Limit @
V
DD
= +4.5 V to +5.5 V
20
10
40
0
40
NOTES
1
All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
Specifications subject to change without notice.
t
CS
CS
t
CH
t
WR
WR
t
DS
DB11–DB0
t
DH
DATA VALID
Figure 3. AD7945 Timing Diagram
AD7948 TIMING SPECIFICATIONS
1
(T = T
A
MIN
to T
MAX
, unless otherwise noted)
Units
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Description
Data Setup Time
Data Hold Time
CSMSB
or
CSLSB
to WR Setup Time
CSMSB
or
CSLSB
to
WR
Hold Time
LDAC
to
WR
Setup Time
LDAC
to WR Hold Time
Write Pulsewidth
Parameter
t
DS
t
DH
t
CWS
t
CWH
t
LWS
t
LWH
t
WR
Limit @
V
DD
= +3 V to +3.6 V
45
10
0
0
0
0
60
Limit @
V
DD
= +4.5 V to +5.5 V
30
10
0
0
0
0
40
NOTES
1
All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
Specifications subject to change without notice.
t
CWS
CSMSB
t
CWH
t
CWS
t
CWH
CSLSB
t
LWS
LDAC
t
LWH
t
WR
WR
t
WR
t
DH
t
DH
DATA
VALID
t
DS
DB7–DB0
DATA
VALID
t
DS
Figure 4. AD7948 Timing Diagram
–6–
REV. B
AD [ ANALOG DEVICES ]
