AD7896
CONVERTER DETAILS
The AD7896 is a fast, 12-bit A/D converter that operates from a
single +2.7 V to +5.5 V supply. It provides the user with a track/
hold, A/D converter and serial interface logic functions on a
single chip. The A/D converter section of the AD7896 consists
of a conventional successive-approximation converter based
around an R-2R ladder structure. The internal reference for the
AD7896 is derived from V
DD
, and this allows the part to accept
an analog input range of 0 V to V
DD
. The AD7896 has two op-
erating modes, the high sampling mode and the auto sleep
mode where the part automatically goes into sleep after the end
of conversion. These modes are discussed in more detail in the
Timing and Control section.
A major advantage of the AD7896 is that it provides all of the
above functions in an 8-pin package, either 8-pin mini-DIP or
SOIC. This offers the user considerable space saving advan-
tages over alternative solutions. The AD7896 consumes only
9 mW typical making it ideal for battery-powered applications.
Conversion is initiated on the AD7896 by pulsing the
CONVST
input. On the falling edge of
CONVST,
the on-chip track/hold
goes from track to hold mode and the conversion sequence is
started. The conversion clock for the part is generated inter-
nally using a laser-trimmed clock oscillator circuit. Conversion
time for the AD7896 is 8
µs
in the high sampling mode
(14
µ
s
for the auto sleep mode),
and the track/hold acquisition time is
1.5
µs.
To obtain optimum performance from the part, the read
operation should not occur during the conversion or during
400 ns prior to the next conversion. This allows the part to op-
erate at throughput rates up to 100 kHz and achieve data sheet
specifications (see Timing and Control Section).
CIRCUIT DESCRIPTION
Analog Input Section
track/hold is greater than the Nyquist rate of the ADC even
when the ADC is operated at its maximum throughput rate of
100 kHz (i.e., the track/hold can handle input frequencies in
excess of 50 kHz).
The track/hold amplifier acquires an input signal to 12-bit accu-
racy in less than 1.5
µs.
The operation of the track/hold is essen-
tially transparent to the user. With the high sampling operating
mode the track/hold amplifier goes from its tracking mode to its
hold mode at the start of conversion (i.e., the rising edge of
CONVST).
The aperture time for the track/hold (i.e., the delay
time between the external
CONVST
signal and the track/hold
actually going into hold) is typically 15 ns. At the end of conver-
sion (on the falling edge of BUSY) the part returns to its
tracking mode. The acquisition time of the track/hold amplifier
begins at this point. For the auto shutdown mode, the rising
edge of
CONVST
wakes up the part and the track and hold
amplifier goes from its tracking mode to its hold mode 6
µs
after
the rising edge of
CONVST
( provided that the
CONVST
high
time is less then 6
µs).
Once again the part returns to its tracking
mode at the end of conversion when the BUSY signal goes low.
Timing and Control Section
The analog input range for the AD7896 is 0 V to V
DD.
The V
IN
pin drives the input to the track/hold amplifier directly. This al-
lows for a maximum output impedance of the circuit driving the
analog input of 1 kΩ. This ensures that the part will be settled
to 12-bit accuracy in the 1.5
µs
acquisition time. This input is
benign with dynamic charging currents. The designed code
transitions occur on successive integer LSB values (i.e., 1 LSB,
2 LSB, 3 LSB . . . FS–1 LSB). Output coding is straight (natu-
ral) binary with 1 LSB = FS/4096 = 3.3 V/4096 = 0.81 mV.
The ideal input/output transfer function is shown in Table I.
Table I. Ideal Input/Output Code Table for the AD7896
Analog Input
1
+FSR – 1 LSB
2
(3.299194)
+FSR – 2 LSB (3.298389)
+FSR/2 – 3 LSB (3.297583)
AGND + 3 LSB (0.002417)
AGND + 2 LSB (0.001611)
AGND + 1 LSB (0.000806)
Code Transition
111 . . . 110 to 111 . . . 111
111 . . . 101 to 111 . . . 110
111 . . . 100 to 111 . . . 101
000 . . . 010 to 000 . . . 011
000 . . . 001 to 000 . . . 010
000 . . . 000 to 000 . . . 001
NOTES
1
FSR is full-scale range and is 3.3 V with V
DD
= +3.3 V.
2
1 LSB = FSR/4096 = 0.81 mV with V
DD
= +3.3 V.
Track/Hold Section
The track/hold amplifier on the analog input of the AD7896 al-
lows the ADC to accurately convert an input sine wave of full-
scale amplitude to 12-bit accuracy. The input bandwidth of the
–6–
Figure 2 shows the timing and control sequence required to ob-
tain optimum performance from the AD7896. In the sequence
shown, conversion is initiated on the falling edge of
CONVST
and new data from this conversion is available in the output reg-
ister of the AD7896 8
µs
later. Once the read operation has
taken place, a further 400 ns should be allowed before the next
falling edge of
CONVST
to optimize the settling of the track/
hold amplifier before the next conversion is initiated. With the
serial clock frequency at its maximum of 10 MHz (5 V opera-
tion), the achievable throughput rate for the part is 8
µs
(conver-
sion time) plus 1.6
µs
(read time) plus 0.4
µs
(acquisition time).
This results in a minimum throughput time of 10
µs
(equivalent
to a throughput rate of 100 kHz). A serial clock of less than 10
MHz can be used but this will in turn mean that the throughput
time will increase.
The read operation consists of sixteen serial clock pulses to the
output shift register of the AD7896. After sixteen serial clock
pulses the shift register is reset and the SDATA line is three-
stated. If there are more serial clock pulses after the sixteenth
clock, the shift register will be moved on past its reset state.
However, the shift register will be reset again on the falling edge
of the
CONVST
signal to ensure that the part returns to a
known state every conversion cycle. As a result, a read opera-
tion from the output register should not straddle across the fall-
ing edge of
CONVST
as the output shift register will be reset in
the middle of the read operation and the data read back into the
microprocessor will appear invalid.
The throughput rate of the part can be increased by reading
data during conversion. If the data is read during conversion, a
throughput time of 8
µs
(conversion time) plus 1.5
µs
(acquisi-
tion time) is achieved when a 10 MHz (5 V operation) serial
clock is being used. This minimum throughput time of 9.5
µs
is
achieved with a slight reduction in performance from the
AD7896. The advantage of this arrangement is that when the
serial clock is significantly lower than 10 MHz the throughput
time for this arrangement will be significantly less than the
throughput time where the data is read after conversion. The
Signal to (Noise + Distortion) number is likely to degrade by
less than 1 dB while the code flicker from the part will also in-
crease (see AD7896 PERFORMANCE section).
REV. B
AD [ ANALOG DEVICES ]
