欢迎访问ic37.com |
会员登录 免费注册
发布采购

AD7892AR-1 参数 Datasheet PDF下载

AD7892AR-1图片预览
型号: AD7892AR-1
PDF下载: 下载PDF文件 查看货源
内容描述: LC2MOS单电源, 12位600 kSPS的ADC [LC2MOS Single Supply, 12-Bit 600 kSPS ADC]
分类和应用:
文件页数/大小: 14 页 / 145 K
品牌: AD [ ANALOG DEVICES ]
 浏览型号AD7892AR-1的Datasheet PDF文件第3页浏览型号AD7892AR-1的Datasheet PDF文件第4页浏览型号AD7892AR-1的Datasheet PDF文件第5页浏览型号AD7892AR-1的Datasheet PDF文件第6页浏览型号AD7892AR-1的Datasheet PDF文件第8页浏览型号AD7892AR-1的Datasheet PDF文件第9页浏览型号AD7892AR-1的Datasheet PDF文件第10页浏览型号AD7892AR-1的Datasheet PDF文件第11页  
AD7892
Pin
No.
16
Mnemonic
DB4/SCLK
Description
Data Bit 4/Serial Clock. When the device is in its parallel mode, this pin is Data Bit 4, a three-state
TTL-compatible output. When the device is in its serial mode, this becomes the serial clock pin,
SCLK. SCLK is an input and an external serial clock must be provided at this pin to obtain serial
data from the AD7892. Serial data is clocked out from the output shift register on the rising edges
of SCLK after
RFS
goes low.
Data Bit 3/Receive Frame Synchronization. When the device is in its parallel mode, this pin is Data
Bit 3, a three-state TTL-compatible output. When the device is in its serial mode, this becomes the
receive frame synchronization input with
RFS
provided externally to obtain serial data from the
AD7892.
Data Bit 2. Three-state TTL-compatible output. This output should be left unconnected when the
device is in its serial mode.
Data Bit 1. Three-state TTL-compatible output. This output should be left unconnected when the
device is in its serial mode.
Data Bit 0 (LSB). Three-state TTL-compatible output. Output coding is two’s complement for
AD7892-1 and AD7892-3 and straight (natural) binary for AD7892-2. This output should be left
unconnected when the device is in its serial mode.
Read. Active low logic input which is used in conjunction with
CS
low to enable the data outputs.
Chip Select. Active low logic input which is used in conjunction with
RD
to enable the data outputs.
End-of-Conversion. Active low logic output indicating converter status. The end of conversion is
signified by a low going pulse on this line. The duration of this
EOC
pulse is nominally 100 ns.
Convert Start. Logic Input. A low-to-high transition on this input puts the track/hold into its hold
mode and starts conversion.
PIN CONFIGURATION
DIP and SOIC
17
DB3/RFS
18
19
20
DB2
DB1
DB0
21
22
23
24
RD
CS
EOC
CONVST
V
DD
STANDBY
V
IN2
V
IN1
REF OUT/REF IN
AGND
MODE
DB11/LOW
DB10/LOW
1
2
3
4
5
6
7
8
9
24 CONVST
23 EOC
22 CS
21 RD
20 DB0 (LSB)
AD7892
19 DB1
TOP VIEW
18 DB2
(Not to Scale)
17 DB3/RFS
16 DB4/SCLK
15 DB5/SDATA
14 DGND
13 DB6
DB9 10
DB8 11
DB7 12
REV. C
–7–