AD7891
Serial Interface Mode
The serial interface mode is selected by tying the MODE input
to a logic low. In this case, five of the data/control inputs of the
parallel mode assume serial interface functions.
The serial interface on the AD7891 is a five-wire interface with
read and write capabilities, with data being read from the output
register via the DATA OUT line and data being written to the
control register via the DATA IN line. The part operates in a
slave or external clocking mode and requires an externally ap-
plied serial clock to the SCLK input to access data from the
data register or write data to the control register. There are
separate framing signals for the read (RFS) and write (TFS)
operations. The serial interface on the AD7891 is designed to
allow the part to be interfaced to systems that provide a serial
clock that is synchronized to the serial data, such as the 80C51,
87C51, 68HC11 and 68HC05 and most digital signal processors.
When using the AD7891 in serial mode, the data lines DB11–
DB10 should be tied to logic low, and the
CS, WR
and
RD
inputs should be tied to logic high. Pins DB4–DB0 can be tied
to either logic high or logic low, but must not be left floating as
this condition could cause the AD7891 to draw large amounts
of current.
Read Operation
remain low for the duration of the data transfer operation. Six-
teen bits of data are transmitted in serial mode with the data
FORMAT bit first, followed by the three address bits in the
control register, followed by the 12-bit conversion result starting
with the MSB. Serial data is clocked out of the device on the
rising edge of SCLK and is valid on the falling edge of SCLK.
At the end of the read operation, the DATA OUT line is three-
stated by a rising edge on either the SCLK or
RFS
inputs, which-
ever occurs first.
Write Operation
Figure 4 shows a write operation to the control register of the
AD7891. The
TFS
input goes low to indicate to the part that a
serial write is about to occur. The AD7891 Control Register
requires only six bits of data. These are loaded on the first six
clock cycles of the serial clock with data on all subsequent clock
cycles being ignored. Serial data to be written to the AD7891
must be valid on the falling edge of SCLK.
Simplifying the Serial Interface
Figure 3 shows the timing diagram for reading from the AD7891
in serial mode.
RFS
goes low to access data from the AD7891.
The serial clock input does not have to be continuous. The serial
data can be accessed in a number of bytes. However,
RFS
must
RFS
(I)
To minimize the number of interconnect lines to the AD7891 in
serial mode, the user can connect the
RFS
and
TFS
lines of the
AD7891 together and read and write from the part simulta-
neously. In this case, new control register data line selecting the
input channel and providing a conversion start command should
be provided on the DATA IN line, while the part provides the
result from the conversion just completed on the DATA OUT
line.
t
11
SCLK (I)
t
13
t
14
t
15
A2
A1
A0
DB11
t
17
t
18
t
18A
DB0
3-STATE
t
12
DATA OUT (O)
FORMAT
NOTE
I = INPUT
O = OUTPUT
t
16
DB10
Figure 3. Serial Mode Read Operation
TFS
(I)
t
19
SCLK (I)
t
22
t
21
t
20
DATA IN (I)
NOTE
I = INPUT
A0
A1
A0
CONV
STBY
FORMAT
DONT
CARE
DONT
CARE
Figure 4. Serial Mode Write Operation
REV. A
–11–
AD [ ANALOG DEVICES ]
