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AD7886JP 参数 Datasheet PDF下载

AD7886JP图片预览
型号: AD7886JP
PDF下载: 下载PDF文件 查看货源
内容描述: LC2MOS 12位, 750千赫/ 1 MHz时,采样ADC [LC2MOS 12-Bit, 750 kHz/1 MHz, Sampling ADC]
分类和应用: 转换器信息通信管理
文件页数/大小: 16 页 / 402 K
品牌: AD [ ANALOG DEVICES ]
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AD7886
PIN CONFIGURATIONS
DIP
DB4
DB5
PLCC
28 DB8
27 DB9
26 DB10
25 DB11
24 V
SS
DGND
DB3
DB2
DB1
DB0
5
6
7
8
9
25 DB11
24 V
SS
DB7
DB10
DB6
DB8
DB9
DB7
DB6
DB5
DB4
DGND
DB3
DB2
DB1
DB0
1
2
3
4
5
6
7
8
9
4
3
2
1
28
27
26
AD7886
TOP VIEW
(Not to Scale)
23 AGND
22 V
REF
21 SUM
20 +5REF
19 V
DD
18 VIN2
17 VIN1
16 AGND
15 V
SS
AD7886
TOP VIEW
(Not to Scale)
23 AGND
22 V
REF
21 SUM
20 +5REF
19 V
DD
V
DD
10
BUSY 11
V
DD
10
BUSY 11
CS 12
RD 13
CONVST 14
12
CS
13
RD
14
CONVST
15
V
SS
16
AGND
17
VIN1
18
VIN2
TERMINOLOGY
Unipolar Offset Error
The ideal first code transition should occur when the analog
input is 1 LSB above AGND. The deviation of the actual transi-
tion from that point is termed the offset error.
Bipolar Zero Error
result. The 12 bits of data are then stored internally in a three-
state output latch.
REFERENCE INPUT
The ideal midscale transition (i.e., 0111 1111 1111 to 1000
0000 0000) for the +5 V range should occur when the analog
input is at zero volts. Bipolar zero error is the deviation of the
actual transition from that point.
Gain Error
In the unipolar mode, gain error is measured with respect to the
first and last code transition points. The ideal difference be-
tween these points is FS–2 LSBs. For bipolar applications, the
gain error is measured from the midscale transition to both the
first and last code transitions. The ideal difference in this case is
FS/2–1 LSB. The gain error is defined as the deviation between
the ideal difference, given above, and the measured difference.
For the bipolar case, there are two gain errors; the figure in the
specification page represents the worst case. Ideal FS depends
on the +5REF input; for the 0 V to 5 V input, ideal FS = +5REF
and for the 0 V to 10 V and +5 V ranges, ideal FS = 2
×
+ 5REF.
CONVERTER DETAILS
The AD7886 operates from a 3.5 V reference, which must be
provided at the V
REF
input. Two on-chip resistors for use with
an external amplifier can be used for deriving 3.5 V from stan-
dard 5 V references. Figure 2 shows an example with the AD586
which a is a high performance voltage reference exhibiting
excellent stability performance, 5 ppm/°C max. The external
amplifier serves a second function of force/sensing the V
REF
input. Force/sensing minimizes error contributions from
+V
+V
IN
V
OUT
+5V
+5REF
R1
9k
SUM
R2
6.3k
V
REF
AD586
GND
AD7886*
AD707
+
–3.5V
The AD7886 is a triple-pass flash ADC that uses 15 compara-
tors in a 4-bit flash technique to perform the 12-bit conversion
procedure. Each of the 4096 quantization levels is realized inter-
nally with a precision resistor DAC.
The fifteen comparators first compare the analog input voltage
to the V
REF
/16 voltages of the resistor array. This determines the
four most significant bits and selects 1 out of 16 voltage seg-
ments. The comparators are then switched to 15 subvoltages on
that segment to determine the next four bits and select 1 out of
256 voltage segments. A further switching of the comparators to
another 15 subvoltages produces the complete 12-bit conversion
REV. B
–5–
C1
10µF
TO DAC
AGND
C2
0.1µF
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 2. Typical Reference Circuitry