Data Sheet
AD7873
SERIAL INTERFACE
updated) and the converter enters conversion mode. At this
Figure 36 shows the typical operation of the serial interface of
the AD7873. The serial clock provides the conversion clock and
also controls the transfer of information to and from the AD7873.
One complete conversion can be achieved with 24 DCLK cycles.
point, track-and-hold goes into hold mode, the input signal is
sampled, and the BUSY output goes high (BUSY returns low on
the next falling edge of DCLK). The internal switches can also
turn off at this point if in single-ended mode, battery-monitor
mode, or temperature measurement mode.
The
signal initiates the data transfer and conversion process.
CS
The falling edge of
takes the BUSY output and the serial bus
CS
The next 12 DCLK cycles are used to perform the conversion
and to clock out the conversion result. If the conversion is
out of three-state. The first eight DCLK cycles are used to write
to the control register via the DIN pin. The control register is
updated in stages as each bit is clocked in. Once the converter
has enough information about the following conversion to set
the input multiplexer and switches appropriately, the converter
enters the acquisition mode and, if required, the internal switches
are turned on. During acquisition mode, the reference input
data is updated. After the three DCLK cycles of acquisition, the
control word is complete (the power management bits are now
ratiometric (SER/
low), the internal switches are on during
DFR
the conversion. A 13th DCLK cycle is needed to allow the
DSP/micro to clock in the LSB. Three more DCLK cycles clock
out the three trailing zeros and complete the 24 DCLK transfer.
The 24 DCLK cycles can be provided from a DSP or via three
bursts of eight clock cycles from a microcontroller.
CS
tACQ
1
8
1
8
1
8
DCLK
DIN
SER/
DFR
S
A2 A1 A0 MODE
IDLE
PD1 PD0
(START)
ACQUIRE
CONVERSION
IDLE
THREE-STATE
THREE-STATE
THREE-STATE
BUSY
DOUT
THREE-STATE
11
(MSB)
10
9
8
7
6
5
4
3
2
1
0
ZERO FILLED
(LSB)
1
X/Y SWITCHES
(SER/DFR HIGH)
OFF
OFF
OFF
ON
1, 2
X/Y SWITCHES
OFF
ON
(SER/DFR LOW)
NOTES
1
Y DRIVERS ARE ON WHEN X+ IS SELECTED INPUT CHANNEL (A2 TO A0 = 001); X DRIVERS ARE ON WHEN Y+ IS SELECTED INPUT CHANNEL (A2 TO A0 = 101).
WHEN PD1, PD0 = 00, 01 OR 10, Y– WILL TURN ON AT THE END OF THE CONVERSION.
2
DRIVERS WILL REMAIN ON IF POWER-DOWN MODE IS 11 (NO POWER-DOWN) UNTIL SELECTED INPUT CHANNEL, REFERENCE MODE,
OR POWER-DOWN MODE IS CHANGED, OR CS IS HIGH.
Figure 36. Conversion Timing, 24 DCLKS per Conversion Cycle, 8-Bit Bus Interface. No DCLK delay required with dedicated serial port.
CS
t9
t4
t6
t6
t1
t10
t5
DCLK
t8
t7
PD0
DIN
t2
t11
t12
BUSY
t3
DOUT
DB11
DB10
Figure 37. Detail Timing Diagram
Rev. F | Page 21 of 28
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