AD7821
In digital signal processing applications, where the AD7821 is
used to sample ac signals, it is essential that the signal sampling
occurs at exactly equal intervals. T his minimizes errors due to
sampling uncertainty or jitter. A precise timer or clock source,
to start the ADC conversion process, is the best method of gen-
erating equidistant sampling intervals.
INT typically goes low within 380 ns after the rising edge of
WR. It indicates that conversion is complete and that the data
result is in the output latch. With CS low, the data outputs
(DB0–DB7) are activated when RD goes low. INT is reset by
the rising edge of RD or CS.
T he two modes of operation given in the data sheet are suitable
for DSP applications because the sampling instant of the
AD7821 is well defined. VIN is sampled on the falling edge of
WR or RD in the WR-RD or RD modes, respectively.
D IGITAL INTERFACE
T he AD7821 has two basic interface modes which are deter-
mined by the status of the MODE pin. When this pin is low, the
converter is in the RD mode, with this pin high, the AD7821 is
set up for the WR-RD mode.
T he RD mode is designed for microprocessors that can be
driven into a WAIT state. A READ operation (i.e., CS and RD
are taken low) starts a conversion and data is read when the
conversion is complete. T he WR-RD mode does not require mi-
croprocessor WAIT states. A WRIT E operation (i.e., CS and
WR are taken low) initiates a conversion, and a READ opera-
tion reads the result when the conversion is complete.
Figure 12a. WR-RD Mode (tRD > tINTL
)
T he alternative option can be used to shorten the conversion
time. T his is a method for bypassing the internal time-out
circuit. T he INT line is ignored and RD can be brought low
250 ns after the rising edge of WR. In this case RD going low
transfers the data result into the output latch and activates the
data output (DB0–DB7). INT is driven low on the falling edge
of RD and is reset on the rising edge of RD or CS. T he timing
for this interface is shown in Figure 12b.
RD Mode (MO D E = 0)
T he timing diagram for the RD mode is shown in Figure 11.
T his mode is intended for use with microprocessors which have
a WAIT state facility, whereby a READ instruction cycle can be
extended to accommodate slow memory devices. A conversion
is started by taking CS and RD low (READ operation). Both
CS and RD are then kept low until output data appears.
Figure 12b. WR-RD Mode (tRD < tINTL
)
T he AD7821 can also be used in stand-alone operation in the
WR-RD mode. CS and RD are tied low, and a conversion is ini-
Figure 11. RD Mode
tiated by bringing WR low. Output data is valid 530 ns (tINT L
ID) after the rising edge of WR. T he timing diagram for this
+
In this mode, Pin 6 of the AD7821 is configured as a status out-
put, RDY. T his RDY output can be used to drive the processor
READY or WAIT input. It is an open drain output (no internal
pull-up device) which goes low after the falling edge of CS and
goes high impedance at the end of conversion. An INT line is
also provided which goes low when a conversion is complete.
INT returns high on the rising edge of CS or RD.
t
mode is shown in Figure 13.
WR-RD Mode (MO D E = 1)
In the WR-RD mode, Pin 6 is configured as a WRIT E (WR) in-
put for the AD7821. With CS low, conversion is initiated on the
falling edge of WR. T wo options exist for reading data from the
converter.
In the first of these options the processor waits for the INT sta-
Figure 13. WR-RD Mode Stand-Alone Operation,
tus line to go low before reading the data (see Figure 12a).
CS = RD = 0
REV. A
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ADI [ ADI ]
