AD7821
MICRO P RO CESSO R INTERFACING
AD 7821 – TMS32010 INTERFACE
T he AD7821 is designed for easy interfacing to microprocessors
as a memory mapped peripheral or an I/O device. T his reduces
to a minimum the amount of external logic required for
interfacing.
A typical interface to the T MS32010 is shown in Figure 16. T he
AD7821 is mapped at a port address and the interface is designed
for the maximum TMS32010 clock frequency of 20 MHz. In this
case, the AD7821 is configured in the WR-RD interface mode.
T his means that a write instruction starts a conversion and a
read instruction reads the result when the conversion is com-
pleted. A precise timer or clock source is used to start a conver-
sion in applications requiring equidistant sampling intervals.
T he scheme used, whereby the AD7821 generates an interrupt
to the T MS32010, is limited in that it does not allow the
AD7821 to be sampled at its maximum rate. T his is because the
time between samples has to be long enough to allow the
T MS32010 to service its interrupt and read data from the
AD7821. Constant interruption of the T MS32010 by the
AD7821, every time the ADC completes a conversion, is not a
very efficient use of the processor time. T o overcome these
problems, some buffer memory or FIFO could be placed be-
tween the AD7821 and the T MS32010. T he INT line of the
AD7821 could be used to trigger a pulse which drives its CS
and RD lines and places the AD7821 data into a FIFO or buffer
memory. T he microprocessor can then read a batch of data
from the FIFO or buffer memory at some convenient time.
Reading data from the AD7821, after an INT has been re-
ceived, consists of <IN A, PA> instruction (PA is the decoded
ADC address).
AD 7821 – 68008 INTERFACE
Figure 14 shows an AD7821 interface to the 68008 micropro-
cessor. T he ADC is configured for the RD interface mode. T his
means that one read instruction starts a conversion and reads
the result when the conversion is completed. T he read cycle is
stretched out over the entire conversion period by taking the
INT line back to the DTACK input of the 68008. Starting a
conversion and reading the relevant data consists of a <MOVE
B Dn, addr> instruction, where addr is the decoded ADC ad-
dress and Dn is the data register into which the result is placed.
Figure 14. AD7821 to 68008 Interface
AD 7821 – 8088 INTERFACE
A typical interface to the 8088 is shown in Figure 15. T he
AD7821 is configured for the RD interface mode. One read in-
struction starts a conversion and reads the result. T he read cycle
is stretched out over the entire conversion period by taking the
RDY line back to the READY input of the 8088. Starting a con-
version and reading the result consists of a <MOV AX, (addr)>
instruction, where addr is the decoded ADC address and AX is
the 8088 data register into which the conversion result is placed.
Figure 16. AD7821 to TMS32010 Interface
AD 7821 – 8051 INTERFACE
Figure 17 shows the AD7821 interface to the 8051 microcom-
puter. T he AD7821 is configured in the WR-RD interface mode
and is connected to the 8051 ports. T he processor starts conver-
sion and then polls INT, until it goes low, before reading the
conversion result. Data is read from the AD7821 by using the
<MOV A, 90H> instruction (90H is the address for Port 1).
Figure 15. AD7821 to 8088 Interface
Figure 17. AD7821 to 8051 Interface
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REV. A
ADI [ ADI ]
