AD7821
TIMING CHARACTERISTICS
1
Parameter
t
CSS
t
CSH
t
RDY2
t
CRD
t
ACC03
t
INTH2
t
DH4
t
P
t
WR
t
RD
t
READ1
t
ACC13
t
RI
t
INTL2
t
READ2
t
ACC23
t
IHWR2
t
ID3
160
185
150
380
500
65
65
90
80
30
45
205
235
185
–
610
75
75
110
100
35
60
240
275
220
–
700
85
85
130
120
40
70
ns max
ns max
ns max
ns typ
ns max
ns min
ns max
ns max
ns max
ns max
ns max
Limit at +25 C
(All Versions)
0
0
70
700
t
CRD
+ 25
t
CRD
+ 50
50
80
15
60
350
250
10
250
160
0
0
85
875
t
CRD
+ 30
t
CRD
+ 65
–
85
15
70
425
325
10
350
205
(V
DD
= +5 V
±
5%, V
SS
= 0 V or –5 V
±
5%; Unipolar or Bipolar Input Range)
Limit at
T
MIN
, T
MAX
(T Version)
0
0
100
975
t
CRD
+ 35
t
CRD
+ 75
–
90
15
80
500
400
10
450
240
Limit at
T
MIN
, T
MAX
(K, B Versions)
Units
ns min
ns min
ns max
ns max
ns max
ns max
ns typ
ns max
ns min
ns max
ns min
ns min
µs
max
ns min
ns min
Conditions/Comments
CS
to
RD/WR
Setup Time
CS
to
RD/WR
Hold Time
CS
to RDY Delay. Pull-Up
Resistor 5 k1.
Conversion Time (RD Mode)
Data Access Time (RD Mode)
C
L
= 20 pF
C
L
= 100 pF
RD
to
INT
Delay (RD Mode)
Data Hold Time
Delay Time Between Conversions
Write Pulse Width
Delay Time between
WR
and
RD
Pulses
RD
Pulse Width (WR-RD Mode, see Figure 12b)
Determined by t
ACC1
Data Access Time (WR-RD Mode, see Figure 12b)
C
L
= 20 pF
C
L
= 100 pF
RD
to
INT
Delay
WR
to
INT
Delay
RD
Pulse Width (WR-RD Mode, see Figure 12a)
Determined by t
ACC2
Data Access Time (WR-RD Mode, see Figure 12a)
C
L
= 20 pF
C
L
= 100 pF
WR
to
INT
Delay (Stand-Alone Operation)
Data Access Time after
INT
(Stand-Alone Operation)
C
L
= 20 pF
C
L
= 100 pF
NOTES
1
Sample tested at +25°C to ensure compliance. All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
2
C
L
= 50 pF.
3
Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4
Defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
Test Circuits
Model
1
AD7821KN
AD7821KP
AD7821KR
AD7821BQ
AD7821TQ
AD7821TE
ORDERING GUIDE
Temperature
Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–55°C to +125°C
Total
Unadjusted Package
Error (LSB) Option
2
±
1 max
±
1 max
±
1 max
±
1 max
±
1 max
±
1 max
N-20
P-20A
R-20
Q-20
Q-20
E-20A
a. High Z to V
OH
b. High Z to V
OL
Figure 1. Load Circuits for Data Access Time Test
NOTES
1
To order MIL-STD-883, Class B processed parts, add /883B to part
number. Contact local sales office for military data sheet.
2
E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded
Chip Carrier; Q = Cerdip; R = SOIC.
a. V
OH
to High Z
b. V
OL
to High Z
Figure 2. Load Circuits for Data Hold Time Test
REV. A
–3–
AD [ ANALOG DEVICES ]
