AD7798/AD7799
TIMING CHARACTERISTICS
Data Sheet
AV
DD
= 2.7 V to 5.25 V, DV
DD
= 2.7 V to 5.25 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DV
DD
, unless otherwise noted.
Table 2.
Parameter
t
3
t
4
Read Operation
t
1
Limit at T
MIN
, T
MAX
(B Version)
100
100
0
60
80
0
60
80
10
80
0
10
0
30
25
0
Unit
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns min
Conditions/Comments
SCLK high pulse width
SCLK low pulse width
CS falling edge to DOUT/RDY active time
DV
DD
= 4.75 V to 5.25 V
DV
DD
= 2.7 V to 3.6 V
SCLK active edge to data valid delay
DV
DD
= 4.75 V to 5.25 V
DV
DD
= 2.7 V to 3.6 V
Bus relinquish time after CS inactive edge
SCLK inactive edge to CS inactive edge
SCLK inactive edge to DOUT/RDY high
CS falling edge to SCLK active edge setup time
Data valid to SCLK edge setup time
Data valid to SCLK edge hold time
CS rising edge to SCLK edge hold time
t
6
t
7
Write Operation
t
8
t
9
t
10
t
11
1
2
Sample tested during initial release to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of DV
DD
) and timed from a voltage level of 1.6 V.
See Figure 3 and Figure 4.
3
These times are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the V
OL
or V
OH
limits.
4
SCLK active edge is the falling edge of SCLK.
5
These times are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured time is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and, as such, are independent of external bus loading capacitances.
6
RDY
returns high after a read of the ADC. In single-conversion mode and continuous-conversion mode, data can be reread, if required, while RDY is high, but care
should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read only once.
I
SINK
(1.6mA WITH DV
DD
= 5V,
100µA WITH DV
DD
= 3V)
TO
OUTPUT
PIN
50pF
1.6V
I
SOURCE
(200µA WITH DV
DD
= 5V,
100µA WITH DV
DD
= 3V)
Figure 2. Load Circuit for Timing Characterization
Rev. B | Page 6 of 28
04856-002
AD [ ANALOG DEVICES ]
