AD7715
Parameter
1
LOGIC OUTPUTS (Including MCLK OUT)
V
OL
, Output Low Voltage
V
OH
, Output High Voltage
Floating State Leakage Current
Floating State Output Capacitance
Data Output Coding
Min
Typ
Max
0.4
DV
DD
− 0.6
±10
9
Binary
Offset binary
Unit
V
V
μA
pF
Unipolar mode
Bipolar mode
Conditions/Comments
I
SINK
= 100 μA except for MCLK OUT
I
SOURCE
= 100 μA except for MCLK OUT
1
2
Temperature range as follows: A version, −40°C to +85°C.
A calibration is effectively a conversion, so these errors are of the order of the conversion noise shown in Table 15 to Table 22. This applies after calibration at the
temperature of interest.
3
Recalibration at any temperature removes these drift errors.
4
Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar and bipolar input ranges.
5
Full-scale drift includes zero-scale drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipolar input ranges.
6
Gain error does not include zero-scale errors. It is calculated as full-scale error–unipolar offset error for unipolar ranges and Full-Scale Error–Bipolar Zero Error for
bipolar ranges.
7
Gain error drift does not include unipolar offset drift/bipolar zero drift. It is effectively the drift of the part if zero scale calibrations only were performed.
8
These numbers are guaranteed by design and/or characterization.
9
This common-mode voltage range is allowed provided that the input voltage on AIN(+) or AIN(−) does not go more positive than AV
DD
+ 30 mV or go more negative
than AGND − 30 mV.
10
The analog input voltage range on AIN(+) is given here with respect to the voltage on AIN(−). The absolute voltage on the analog inputs should not go more positive
than AV
DD
+ 30 mV or go more negative than AGND − 30 mV.
11
V
REF
= REF IN(+) − REF IN(−).
12
These logic output levels apply to the MCLK OUT only when it is loaded with one CMOS load.
13
Sample tested at 25°C to ensure compliance.
Rev. D | Page 6 of 40
AD [ ANALOG DEVICES ]
